(ModbusSlave): добавил тест проверки accessmode.

extensions/ModbusSlave/MBSlave.cc

@@ -830,8 +830,8 @@ bool MBSlave::initItem( UniXML_iterator& it )
     string am(IOBase::initProp(it,"accessmode",prop_prefix,false));
     if( am == "ro" )
         p.amode = MBSlave::amRO;
-    else if( am == "rw" )
-        p.amode = MBSlave::amRW;
+    else if( am == "wo" )
+        p.amode = MBSlave::amWO;
 
     string vt(IOBase::initProp(it,"vtype",prop_prefix,false));
     if( vt.empty() )

extensions/ModbusSlave/tests/mbslave-test-configure.xml

@@ -148,6 +148,11 @@
 			<item default="65534" id="2012" mbs="1" mbreg="119" iotype="AI" vtype="unsigned" name="TestVtype12" textname="Тестовый регистр для проверки vtype"/>
 			<item id="2013" rawdata="1" mbs="1" mbreg="120" iotype="AI" vtype="F4" name="TestVtype9" textname="Тестовый регистр для проверки vtype"/>
 			
+			<!-- access mode test -->
+			<item id="2014" default="1002" accessmode="ro" mbs="1" mbreg="124" iotype="AI" name="TestAccessMode1" textname="Тестовый регистр для проверки access mode"/>
+			<item id="2015" default="2222" accessmode="wo" mbs="1" mbreg="125" iotype="AI" name="TestAccessMode2" textname="Тестовый регистр для проверки access mode"/>
+			<item id="2016" default="1000" accessmode="rw" mbs="1" mbreg="126" iotype="AI" name="TestAccessMode3" textname="Тестовый регистр для проверки access mode"/>
+
 			<item id="10000" iotype="DI" name="TestMode_S" textname="Тестовый датчик"/>
 
 		</sensors>

extensions/ModbusSlave/tests/mbslave-tests.cc

@@ -805,5 +805,62 @@ TEST_CASE("(0x66): file transfer")
 
 TEST_CASE("access mode","[modbus][mbslvae][mbtcpslave]")
 {
+	SECTION("test 'RO' register")
+	{
+		ModbusRTU::ModbusData tREG=124;
+
+		// read
+		ModbusRTU::ReadInputRetMessage ret = mb->read04(slaveaddr,tREG,1);
+		REQUIRE( ret.data[0] == 1002 );
+
+		// write
+		try
+		{
+			ModbusRTU::WriteOutputMessage msg(slaveaddr,tREG);
+			msg.addData(33);
+			mb->write10(msg);
+		}
+		catch( ModbusRTU::mbException& ex )
+		{
+			REQUIRE( ex.err == ModbusRTU::erBadDataAddress );
+		}
+	}
+	SECTION("test 'WO' register")
+	{
+		ModbusRTU::ModbusData tREG=125;
+
+		// read
+		try
+		{
+			mb->read04(slaveaddr,tREG,1);
+		}
+		catch( ModbusRTU::mbException& ex )
+		{
+			REQUIRE( ex.err == ModbusRTU::erBadDataAddress );
+		}
+		
+		// write
+		ModbusRTU::WriteOutputMessage msg(slaveaddr,tREG);
+		msg.addData(555);
+		ModbusRTU::WriteOutputRetMessage ret = mb->write10(msg);
+		REQUIRE( ret.start == tREG );
+		REQUIRE( ret.quant == 1 );
+		REQUIRE( ui->getValue(2015) == 555 );
+	}
+	SECTION("test 'RW' register")
+	{
+		ModbusRTU::ModbusData tREG=126;
 
+		// write
+		ModbusRTU::WriteOutputMessage msg(slaveaddr,tREG);
+		msg.addData(555);
+		ModbusRTU::WriteOutputRetMessage ret = mb->write10(msg);
+		REQUIRE( ret.start == tREG );
+		REQUIRE( ret.quant == 1 );
+		REQUIRE( ui->getValue(2016) == 555 );
+
+		// read
+		ModbusRTU::ReadInputRetMessage rret = mb->read04(slaveaddr,tREG,1);
+		REQUIRE( rret.data[0] == 555 );
+	}
 }
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