Commit bd6ae2f4 authored by Józef Kucia's avatar Józef Kucia Committed by Alexandre Julliard

wined3d: Handle raw thread group shared memory declarations.

parent 10b36e39
...@@ -6833,6 +6833,7 @@ static GLuint shader_glsl_generate_compute_shader(const struct wined3d_context * ...@@ -6833,6 +6833,7 @@ static GLuint shader_glsl_generate_compute_shader(const struct wined3d_context *
const struct wined3d_gl_info *gl_info = context->gl_info; const struct wined3d_gl_info *gl_info = context->gl_info;
struct shader_glsl_ctx_priv priv_ctx; struct shader_glsl_ctx_priv priv_ctx;
GLuint shader_id; GLuint shader_id;
unsigned int i;
shader_id = GL_EXTCALL(glCreateShader(GL_COMPUTE_SHADER)); shader_id = GL_EXTCALL(glCreateShader(GL_COMPUTE_SHADER));
...@@ -6846,6 +6847,12 @@ static GLuint shader_glsl_generate_compute_shader(const struct wined3d_context * ...@@ -6846,6 +6847,12 @@ static GLuint shader_glsl_generate_compute_shader(const struct wined3d_context *
priv_ctx.string_buffers = string_buffers; priv_ctx.string_buffers = string_buffers;
shader_generate_glsl_declarations(context, buffer, shader, reg_maps, &priv_ctx); shader_generate_glsl_declarations(context, buffer, shader, reg_maps, &priv_ctx);
for (i = 0; i < reg_maps->tgsm_count; ++i)
{
if (reg_maps->tgsm[i].size)
shader_addline(buffer, "shared uint cs_g%u[%u];\n", i, reg_maps->tgsm[i].size);
}
shader_addline(buffer, "layout(local_size_x = %u, local_size_y = %u, local_size_z = %u) in;\n", shader_addline(buffer, "layout(local_size_x = %u, local_size_y = %u, local_size_z = %u) in;\n",
thread_group_size->x, thread_group_size->y, thread_group_size->z); thread_group_size->x, thread_group_size->y, thread_group_size->z);
...@@ -9454,7 +9461,7 @@ static const SHADER_HANDLER shader_glsl_instruction_handler_table[WINED3DSIH_TAB ...@@ -9454,7 +9461,7 @@ static const SHADER_HANDLER shader_glsl_instruction_handler_table[WINED3DSIH_TAB
/* WINED3DSIH_DCL_TESSELLATOR_DOMAIN */ NULL, /* WINED3DSIH_DCL_TESSELLATOR_DOMAIN */ NULL,
/* WINED3DSIH_DCL_TESSELLATOR_OUTPUT_PRIMITIVE */ NULL, /* WINED3DSIH_DCL_TESSELLATOR_OUTPUT_PRIMITIVE */ NULL,
/* WINED3DSIH_DCL_TESSELLATOR_PARTITIONING */ NULL, /* WINED3DSIH_DCL_TESSELLATOR_PARTITIONING */ NULL,
/* WINED3DSIH_DCL_TGSM_RAW */ NULL, /* WINED3DSIH_DCL_TGSM_RAW */ shader_glsl_nop,
/* WINED3DSIH_DCL_TGSM_STRUCTURED */ NULL, /* WINED3DSIH_DCL_TGSM_STRUCTURED */ NULL,
/* WINED3DSIH_DCL_THREAD_GROUP */ shader_glsl_nop, /* WINED3DSIH_DCL_THREAD_GROUP */ shader_glsl_nop,
/* WINED3DSIH_DCL_UAV_RAW */ shader_glsl_nop, /* WINED3DSIH_DCL_UAV_RAW */ shader_glsl_nop,
......
...@@ -1047,6 +1047,31 @@ static HRESULT shader_get_registers_used(struct wined3d_shader *shader, const st ...@@ -1047,6 +1047,31 @@ static HRESULT shader_get_registers_used(struct wined3d_shader *shader, const st
{ {
reg_maps->temporary_count = ins.declaration.count; reg_maps->temporary_count = ins.declaration.count;
} }
else if (ins.handler_idx == WINED3DSIH_DCL_TGSM_RAW)
{
unsigned int reg_idx = ins.declaration.tgsm_raw.reg.reg.idx[0].offset;
if (reg_idx >= MAX_TGSM_REGISTERS)
{
ERR("Invalid TGSM register index %u.\n", reg_idx);
break;
}
if (shader_version.type == WINED3D_SHADER_TYPE_COMPUTE)
{
struct wined3d_shader_tgsm *tgsm;
if (!wined3d_array_reserve((void **)&reg_maps->tgsm, &reg_maps->tgsm_capacity,
reg_idx + 1, sizeof(*reg_maps->tgsm)))
return E_OUTOFMEMORY;
reg_maps->tgsm_count = reg_idx + 1;
tgsm = &reg_maps->tgsm[reg_idx];
tgsm->size = ins.declaration.tgsm_raw.byte_count / 4;
}
else
{
FIXME("Invalid instruction %#x for shader type %#x.\n",
ins.handler_idx, shader_version.type);
}
}
else if (ins.handler_idx == WINED3DSIH_DCL_THREAD_GROUP) else if (ins.handler_idx == WINED3DSIH_DCL_THREAD_GROUP)
{ {
if (shader_version.type == WINED3D_SHADER_TYPE_COMPUTE) if (shader_version.type == WINED3D_SHADER_TYPE_COMPUTE)
...@@ -1522,6 +1547,8 @@ static void shader_cleanup_reg_maps(struct wined3d_shader_reg_maps *reg_maps) ...@@ -1522,6 +1547,8 @@ static void shader_cleanup_reg_maps(struct wined3d_shader_reg_maps *reg_maps)
LIST_FOR_EACH_ENTRY_SAFE(reg, reg_next, &reg_maps->indexable_temps, struct wined3d_shader_indexable_temp, entry) LIST_FOR_EACH_ENTRY_SAFE(reg, reg_next, &reg_maps->indexable_temps, struct wined3d_shader_indexable_temp, entry)
HeapFree(GetProcessHeap(), 0, reg); HeapFree(GetProcessHeap(), 0, reg);
list_init(&reg_maps->indexable_temps); list_init(&reg_maps->indexable_temps);
HeapFree(GetProcessHeap(), 0, reg_maps->tgsm);
} }
unsigned int shader_find_free_input_register(const struct wined3d_shader_reg_maps *reg_maps, unsigned int max) unsigned int shader_find_free_input_register(const struct wined3d_shader_reg_maps *reg_maps, unsigned int max)
......
...@@ -763,6 +763,8 @@ static void shader_sm5_read_dcl_tgsm_raw(struct wined3d_shader_instruction *ins, ...@@ -763,6 +763,8 @@ static void shader_sm5_read_dcl_tgsm_raw(struct wined3d_shader_instruction *ins,
{ {
shader_sm4_read_dst_param(priv, &tokens, WINED3D_DATA_FLOAT, &ins->declaration.tgsm_raw.reg); shader_sm4_read_dst_param(priv, &tokens, WINED3D_DATA_FLOAT, &ins->declaration.tgsm_raw.reg);
ins->declaration.tgsm_raw.byte_count = *tokens; ins->declaration.tgsm_raw.byte_count = *tokens;
if (ins->declaration.tgsm_raw.byte_count % 4)
FIXME("Byte count %u is not multiple of 4.\n", ins->declaration.tgsm_raw.byte_count);
} }
static void shader_sm5_read_dcl_tgsm_structured(struct wined3d_shader_instruction *ins, static void shader_sm5_read_dcl_tgsm_structured(struct wined3d_shader_instruction *ins,
......
...@@ -185,6 +185,7 @@ static inline enum complex_fixup get_complex_fixup(struct color_fixup_desc fixup ...@@ -185,6 +185,7 @@ static inline enum complex_fixup get_complex_fixup(struct color_fixup_desc fixup
#define MAX_SAMPLER_OBJECTS 16 #define MAX_SAMPLER_OBJECTS 16
#define MAX_SHADER_RESOURCE_VIEWS 128 #define MAX_SHADER_RESOURCE_VIEWS 128
#define MAX_UNORDERED_ACCESS_VIEWS 8 #define MAX_UNORDERED_ACCESS_VIEWS 8
#define MAX_TGSM_REGISTERS 8192
#define MAX_VERTEX_BLENDS 4 #define MAX_VERTEX_BLENDS 4
#define MAX_MULTISAMPLE_TYPES 8 #define MAX_MULTISAMPLE_TYPES 8
...@@ -915,6 +916,10 @@ struct wined3d_shader_reg_maps ...@@ -915,6 +916,10 @@ struct wined3d_shader_reg_maps
/* Whether or not loops are used in this shader, and nesting depth */ /* Whether or not loops are used in this shader, and nesting depth */
unsigned loop_depth; unsigned loop_depth;
UINT min_rel_offset, max_rel_offset; UINT min_rel_offset, max_rel_offset;
struct wined3d_shader_tgsm *tgsm;
SIZE_T tgsm_capacity;
unsigned int tgsm_count;
}; };
/* Keeps track of details for TEX_M#x# instructions which need to maintain /* Keeps track of details for TEX_M#x# instructions which need to maintain
...@@ -998,6 +1003,11 @@ struct wined3d_shader_structured_resource ...@@ -998,6 +1003,11 @@ struct wined3d_shader_structured_resource
unsigned int byte_stride; unsigned int byte_stride;
}; };
struct wined3d_shader_tgsm
{
unsigned int size;
};
struct wined3d_shader_tgsm_raw struct wined3d_shader_tgsm_raw
{ {
struct wined3d_shader_dst_param reg; struct wined3d_shader_dst_param reg;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment