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wine
wine-cw
Commits
fd6ea955
Commit
fd6ea955
authored
Apr 03, 2020
by
Rémi Bernon
Committed by
Alexandre Julliard
Apr 03, 2020
Browse files
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Browse Files
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Plain Diff
winedbg: Remove the use of gdb specific register length.
Signed-off-by:
Rémi Bernon
<
rbernon@codeweavers.com
>
Signed-off-by:
Alexandre Julliard
<
julliard@winehq.org
>
parent
99b7e2bb
Hide whitespace changes
Inline
Side-by-side
Showing
7 changed files
with
236 additions
and
275 deletions
+236
-275
be_arm.c
programs/winedbg/be_arm.c
+18
-18
be_arm64.c
programs/winedbg/be_arm64.c
+35
-35
be_cpu.h
programs/winedbg/be_cpu.h
+2
-3
be_i386.c
programs/winedbg/be_i386.c
+43
-43
be_ppc.c
programs/winedbg/be_ppc.c
+73
-73
be_x86_64.c
programs/winedbg/be_x86_64.c
+59
-59
gdbproxy.c
programs/winedbg/gdbproxy.c
+6
-44
No files found.
programs/winedbg/be_arm.c
View file @
fd6ea955
...
...
@@ -1900,26 +1900,26 @@ static BOOL be_arm_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
}
#define REG(f,n,t,r
,gs) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs
}
#define REG(f,n,t,r
) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r)
}
static
struct
gdb_register
be_arm_gdb_register_map
[]
=
{
REG
(
"core"
,
"r0"
,
NULL
,
R0
,
4
),
REG
(
NULL
,
"r1"
,
NULL
,
R1
,
4
),
REG
(
NULL
,
"r2"
,
NULL
,
R2
,
4
),
REG
(
NULL
,
"r3"
,
NULL
,
R3
,
4
),
REG
(
NULL
,
"r4"
,
NULL
,
R4
,
4
),
REG
(
NULL
,
"r5"
,
NULL
,
R5
,
4
),
REG
(
NULL
,
"r6"
,
NULL
,
R6
,
4
),
REG
(
NULL
,
"r7"
,
NULL
,
R7
,
4
),
REG
(
NULL
,
"r8"
,
NULL
,
R8
,
4
),
REG
(
NULL
,
"r9"
,
NULL
,
R9
,
4
),
REG
(
NULL
,
"r10"
,
NULL
,
R10
,
4
),
REG
(
NULL
,
"r11"
,
NULL
,
R11
,
4
),
REG
(
NULL
,
"r12"
,
NULL
,
R12
,
4
),
REG
(
NULL
,
"sp"
,
"data_ptr"
,
Sp
,
4
),
REG
(
NULL
,
"lr"
,
"code_ptr"
,
Lr
,
4
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Pc
,
4
),
REG
(
NULL
,
"cpsr"
,
NULL
,
Cpsr
,
4
),
REG
(
"core"
,
"r0"
,
NULL
,
R0
),
REG
(
NULL
,
"r1"
,
NULL
,
R1
),
REG
(
NULL
,
"r2"
,
NULL
,
R2
),
REG
(
NULL
,
"r3"
,
NULL
,
R3
),
REG
(
NULL
,
"r4"
,
NULL
,
R4
),
REG
(
NULL
,
"r5"
,
NULL
,
R5
),
REG
(
NULL
,
"r6"
,
NULL
,
R6
),
REG
(
NULL
,
"r7"
,
NULL
,
R7
),
REG
(
NULL
,
"r8"
,
NULL
,
R8
),
REG
(
NULL
,
"r9"
,
NULL
,
R9
),
REG
(
NULL
,
"r10"
,
NULL
,
R10
),
REG
(
NULL
,
"r11"
,
NULL
,
R11
),
REG
(
NULL
,
"r12"
,
NULL
,
R12
),
REG
(
NULL
,
"sp"
,
"data_ptr"
,
Sp
),
REG
(
NULL
,
"lr"
,
"code_ptr"
,
Lr
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Pc
),
REG
(
NULL
,
"cpsr"
,
NULL
,
Cpsr
),
};
struct
backend_cpu
be_arm
=
...
...
programs/winedbg/be_arm64.c
View file @
fd6ea955
...
...
@@ -289,43 +289,43 @@ static BOOL be_arm64_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
}
#define REG(f,n,t,r
,gs) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs
}
#define REG(f,n,t,r
) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r)
}
static
struct
gdb_register
be_arm64_gdb_register_map
[]
=
{
REG
(
"core"
,
"x0"
,
NULL
,
u
.
s
.
X0
,
8
),
REG
(
NULL
,
"x1"
,
NULL
,
u
.
s
.
X1
,
8
),
REG
(
NULL
,
"x2"
,
NULL
,
u
.
s
.
X2
,
8
),
REG
(
NULL
,
"x3"
,
NULL
,
u
.
s
.
X3
,
8
),
REG
(
NULL
,
"x4"
,
NULL
,
u
.
s
.
X4
,
8
),
REG
(
NULL
,
"x5"
,
NULL
,
u
.
s
.
X5
,
8
),
REG
(
NULL
,
"x6"
,
NULL
,
u
.
s
.
X6
,
8
),
REG
(
NULL
,
"x7"
,
NULL
,
u
.
s
.
X7
,
8
),
REG
(
NULL
,
"x8"
,
NULL
,
u
.
s
.
X8
,
8
),
REG
(
NULL
,
"x9"
,
NULL
,
u
.
s
.
X9
,
8
),
REG
(
NULL
,
"x10"
,
NULL
,
u
.
s
.
X10
,
8
),
REG
(
NULL
,
"x11"
,
NULL
,
u
.
s
.
X11
,
8
),
REG
(
NULL
,
"x12"
,
NULL
,
u
.
s
.
X12
,
8
),
REG
(
NULL
,
"x13"
,
NULL
,
u
.
s
.
X13
,
8
),
REG
(
NULL
,
"x14"
,
NULL
,
u
.
s
.
X14
,
8
),
REG
(
NULL
,
"x15"
,
NULL
,
u
.
s
.
X15
,
8
),
REG
(
NULL
,
"x16"
,
NULL
,
u
.
s
.
X16
,
8
),
REG
(
NULL
,
"x17"
,
NULL
,
u
.
s
.
X17
,
8
),
REG
(
NULL
,
"x18"
,
NULL
,
u
.
s
.
X18
,
8
),
REG
(
NULL
,
"x19"
,
NULL
,
u
.
s
.
X19
,
8
),
REG
(
NULL
,
"x20"
,
NULL
,
u
.
s
.
X20
,
8
),
REG
(
NULL
,
"x21"
,
NULL
,
u
.
s
.
X21
,
8
),
REG
(
NULL
,
"x22"
,
NULL
,
u
.
s
.
X22
,
8
),
REG
(
NULL
,
"x23"
,
NULL
,
u
.
s
.
X23
,
8
),
REG
(
NULL
,
"x24"
,
NULL
,
u
.
s
.
X24
,
8
),
REG
(
NULL
,
"x25"
,
NULL
,
u
.
s
.
X25
,
8
),
REG
(
NULL
,
"x26"
,
NULL
,
u
.
s
.
X26
,
8
),
REG
(
NULL
,
"x27"
,
NULL
,
u
.
s
.
X27
,
8
),
REG
(
NULL
,
"x28"
,
NULL
,
u
.
s
.
X28
,
8
),
REG
(
NULL
,
"x29"
,
NULL
,
u
.
s
.
Fp
,
8
),
REG
(
NULL
,
"x30"
,
NULL
,
u
.
s
.
Lr
,
8
),
REG
(
NULL
,
"sp"
,
"data_ptr"
,
Sp
,
8
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Pc
,
8
),
REG
(
NULL
,
"cpsr"
,
"cpsr_flags"
,
Cpsr
,
4
),
REG
(
"core"
,
"x0"
,
NULL
,
u
.
s
.
X0
),
REG
(
NULL
,
"x1"
,
NULL
,
u
.
s
.
X1
),
REG
(
NULL
,
"x2"
,
NULL
,
u
.
s
.
X2
),
REG
(
NULL
,
"x3"
,
NULL
,
u
.
s
.
X3
),
REG
(
NULL
,
"x4"
,
NULL
,
u
.
s
.
X4
),
REG
(
NULL
,
"x5"
,
NULL
,
u
.
s
.
X5
),
REG
(
NULL
,
"x6"
,
NULL
,
u
.
s
.
X6
),
REG
(
NULL
,
"x7"
,
NULL
,
u
.
s
.
X7
),
REG
(
NULL
,
"x8"
,
NULL
,
u
.
s
.
X8
),
REG
(
NULL
,
"x9"
,
NULL
,
u
.
s
.
X9
),
REG
(
NULL
,
"x10"
,
NULL
,
u
.
s
.
X10
),
REG
(
NULL
,
"x11"
,
NULL
,
u
.
s
.
X11
),
REG
(
NULL
,
"x12"
,
NULL
,
u
.
s
.
X12
),
REG
(
NULL
,
"x13"
,
NULL
,
u
.
s
.
X13
),
REG
(
NULL
,
"x14"
,
NULL
,
u
.
s
.
X14
),
REG
(
NULL
,
"x15"
,
NULL
,
u
.
s
.
X15
),
REG
(
NULL
,
"x16"
,
NULL
,
u
.
s
.
X16
),
REG
(
NULL
,
"x17"
,
NULL
,
u
.
s
.
X17
),
REG
(
NULL
,
"x18"
,
NULL
,
u
.
s
.
X18
),
REG
(
NULL
,
"x19"
,
NULL
,
u
.
s
.
X19
),
REG
(
NULL
,
"x20"
,
NULL
,
u
.
s
.
X20
),
REG
(
NULL
,
"x21"
,
NULL
,
u
.
s
.
X21
),
REG
(
NULL
,
"x22"
,
NULL
,
u
.
s
.
X22
),
REG
(
NULL
,
"x23"
,
NULL
,
u
.
s
.
X23
),
REG
(
NULL
,
"x24"
,
NULL
,
u
.
s
.
X24
),
REG
(
NULL
,
"x25"
,
NULL
,
u
.
s
.
X25
),
REG
(
NULL
,
"x26"
,
NULL
,
u
.
s
.
X26
),
REG
(
NULL
,
"x27"
,
NULL
,
u
.
s
.
X27
),
REG
(
NULL
,
"x28"
,
NULL
,
u
.
s
.
X28
),
REG
(
NULL
,
"x29"
,
NULL
,
u
.
s
.
Fp
),
REG
(
NULL
,
"x30"
,
NULL
,
u
.
s
.
Lr
),
REG
(
NULL
,
"sp"
,
"data_ptr"
,
Sp
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Pc
),
REG
(
NULL
,
"cpsr"
,
"cpsr_flags"
,
Cpsr
),
};
struct
backend_cpu
be_arm64
=
...
...
programs/winedbg/be_cpu.h
View file @
fd6ea955
...
...
@@ -27,9 +27,8 @@ struct gdb_register
const
char
*
feature
;
const
char
*
name
;
const
char
*
type
;
size_t
ctx_offset
;
size_t
ctx_length
;
size_t
gdb_length
;
size_t
offset
;
size_t
length
;
};
struct
backend_cpu
...
...
programs/winedbg/be_i386.c
View file @
fd6ea955
...
...
@@ -865,51 +865,51 @@ static BOOL be_i386_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
Wow64SetThreadContext
(
thread
,
&
ctx
->
x86
);
}
#define REG(f,n,t,r
,gs) {f, n, t, FIELD_OFFSET(WOW64_CONTEXT, r), sizeof(((WOW64_CONTEXT*)NULL)->r), gs
}
#define REG(f,n,t,r
) {f, n, t, FIELD_OFFSET(WOW64_CONTEXT, r), sizeof(((WOW64_CONTEXT*)NULL)->r)
}
static
struct
gdb_register
be_i386_gdb_register_map
[]
=
{
REG
(
"core"
,
"eax"
,
NULL
,
Eax
,
4
),
REG
(
NULL
,
"ecx"
,
NULL
,
Ecx
,
4
),
REG
(
NULL
,
"edx"
,
NULL
,
Edx
,
4
),
REG
(
NULL
,
"ebx"
,
NULL
,
Ebx
,
4
),
REG
(
NULL
,
"esp"
,
"data_ptr"
,
Esp
,
4
),
REG
(
NULL
,
"ebp"
,
"data_ptr"
,
Ebp
,
4
),
REG
(
NULL
,
"esi"
,
NULL
,
Esi
,
4
),
REG
(
NULL
,
"edi"
,
NULL
,
Edi
,
4
),
REG
(
NULL
,
"eip"
,
"code_ptr"
,
Eip
,
4
),
REG
(
NULL
,
"eflags"
,
"i386_eflags"
,
EFlags
,
4
),
REG
(
NULL
,
"cs"
,
NULL
,
SegCs
,
4
),
REG
(
NULL
,
"ss"
,
NULL
,
SegSs
,
4
),
REG
(
NULL
,
"ds"
,
NULL
,
SegDs
,
4
),
REG
(
NULL
,
"es"
,
NULL
,
SegEs
,
4
),
REG
(
NULL
,
"fs"
,
NULL
,
SegFs
,
4
),
REG
(
NULL
,
"gs"
,
NULL
,
SegGs
,
4
),
{
NULL
,
"st0"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
0
]),
10
,
10
},
{
NULL
,
"st1"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
10
]),
10
,
10
},
{
NULL
,
"st2"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
20
]),
10
,
10
},
{
NULL
,
"st3"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
30
]),
10
,
10
},
{
NULL
,
"st4"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
40
]),
10
,
10
},
{
NULL
,
"st5"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
50
]),
10
,
10
},
{
NULL
,
"st6"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
60
]),
10
,
10
},
{
NULL
,
"st7"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
70
]),
10
,
10
},
{
NULL
,
"fctrl"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ControlWord
),
2
,
4
},
{
NULL
,
"fstat"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
StatusWord
),
2
,
4
},
{
NULL
,
"ftag"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
TagWord
),
2
,
4
},
{
NULL
,
"fiseg"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ErrorSelector
),
2
,
4
},
REG
(
NULL
,
"fioff"
,
NULL
,
FloatSave
.
ErrorOffset
,
4
),
{
NULL
,
"foseg"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
DataSelector
),
2
,
4
},
REG
(
NULL
,
"fooff"
,
NULL
,
FloatSave
.
DataOffset
,
4
),
{
NULL
,
"fop"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ErrorSelector
)
+
2
,
2
,
4
},
{
"sse"
,
"xmm0"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
0
]),
16
,
16
},
{
NULL
,
"xmm1"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
1
]),
16
,
16
},
{
NULL
,
"xmm2"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
2
]),
16
,
16
},
{
NULL
,
"xmm3"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
3
]),
16
,
16
},
{
NULL
,
"xmm4"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
4
]),
16
,
16
},
{
NULL
,
"xmm5"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
5
]),
16
,
16
},
{
NULL
,
"xmm6"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
6
]),
16
,
16
},
{
NULL
,
"xmm7"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
7
]),
16
,
16
},
{
NULL
,
"mxcsr"
,
"i386_mxcsr"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
MxCsr
),
4
,
4
},
REG
(
"core"
,
"eax"
,
NULL
,
Eax
),
REG
(
NULL
,
"ecx"
,
NULL
,
Ecx
),
REG
(
NULL
,
"edx"
,
NULL
,
Edx
),
REG
(
NULL
,
"ebx"
,
NULL
,
Ebx
),
REG
(
NULL
,
"esp"
,
"data_ptr"
,
Esp
),
REG
(
NULL
,
"ebp"
,
"data_ptr"
,
Ebp
),
REG
(
NULL
,
"esi"
,
NULL
,
Esi
),
REG
(
NULL
,
"edi"
,
NULL
,
Edi
),
REG
(
NULL
,
"eip"
,
"code_ptr"
,
Eip
),
REG
(
NULL
,
"eflags"
,
"i386_eflags"
,
EFlags
),
REG
(
NULL
,
"cs"
,
NULL
,
SegCs
),
REG
(
NULL
,
"ss"
,
NULL
,
SegSs
),
REG
(
NULL
,
"ds"
,
NULL
,
SegDs
),
REG
(
NULL
,
"es"
,
NULL
,
SegEs
),
REG
(
NULL
,
"fs"
,
NULL
,
SegFs
),
REG
(
NULL
,
"gs"
,
NULL
,
SegGs
),
{
NULL
,
"st0"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
0
]),
10
},
{
NULL
,
"st1"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
10
]),
10
},
{
NULL
,
"st2"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
20
]),
10
},
{
NULL
,
"st3"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
30
]),
10
},
{
NULL
,
"st4"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
40
]),
10
},
{
NULL
,
"st5"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
50
]),
10
},
{
NULL
,
"st6"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
60
]),
10
},
{
NULL
,
"st7"
,
"i387_ext"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
RegisterArea
[
70
]),
10
},
{
NULL
,
"fctrl"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ControlWord
),
2
},
{
NULL
,
"fstat"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
StatusWord
),
2
},
{
NULL
,
"ftag"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
TagWord
),
2
},
{
NULL
,
"fiseg"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ErrorSelector
),
2
},
REG
(
NULL
,
"fioff"
,
NULL
,
FloatSave
.
ErrorOffset
),
{
NULL
,
"foseg"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
DataSelector
),
2
},
REG
(
NULL
,
"fooff"
,
NULL
,
FloatSave
.
DataOffset
),
{
NULL
,
"fop"
,
NULL
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
FloatSave
.
ErrorSelector
)
+
2
,
2
},
{
"sse"
,
"xmm0"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
0
]),
16
},
{
NULL
,
"xmm1"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
1
]),
16
},
{
NULL
,
"xmm2"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
2
]),
16
},
{
NULL
,
"xmm3"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
3
]),
16
},
{
NULL
,
"xmm4"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
4
]),
16
},
{
NULL
,
"xmm5"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
5
]),
16
},
{
NULL
,
"xmm6"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
6
]),
16
},
{
NULL
,
"xmm7"
,
"vec128"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
XmmRegisters
[
7
]),
16
},
{
NULL
,
"mxcsr"
,
"i386_mxcsr"
,
FIELD_OFFSET
(
WOW64_CONTEXT
,
ExtendedRegisters
)
+
FIELD_OFFSET
(
XMM_SAVE_AREA32
,
MxCsr
),
4
},
};
struct
backend_cpu
be_i386
=
...
...
programs/winedbg/be_ppc.c
View file @
fd6ea955
...
...
@@ -191,81 +191,81 @@ static BOOL be_ppc_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
}
#define REG(f,n,t,r
,gs) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs
}
#define REG(f,n,t,r
) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r)
}
static
struct
gdb_register
be_ppc_gdb_register_map
[]
=
{
REG
(
"core"
,
"r0"
,
NULL
,
Gpr0
,
4
),
REG
(
NULL
,
"r1"
,
NULL
,
Gpr1
,
4
),
REG
(
NULL
,
"r2"
,
NULL
,
Gpr2
,
4
),
REG
(
NULL
,
"r3"
,
NULL
,
Gpr3
,
4
),
REG
(
NULL
,
"r4"
,
NULL
,
Gpr4
,
4
),
REG
(
NULL
,
"r5"
,
NULL
,
Gpr5
,
4
),
REG
(
NULL
,
"r6"
,
NULL
,
Gpr6
,
4
),
REG
(
NULL
,
"r7"
,
NULL
,
Gpr7
,
4
),
REG
(
NULL
,
"r8"
,
NULL
,
Gpr8
,
4
),
REG
(
NULL
,
"r9"
,
NULL
,
Gpr9
,
4
),
REG
(
NULL
,
"r10"
,
NULL
,
Gpr10
,
4
),
REG
(
NULL
,
"r11"
,
NULL
,
Gpr11
,
4
),
REG
(
NULL
,
"r12"
,
NULL
,
Gpr12
,
4
),
REG
(
NULL
,
"r13"
,
NULL
,
Gpr13
,
4
),
REG
(
NULL
,
"r14"
,
NULL
,
Gpr14
,
4
),
REG
(
NULL
,
"r15"
,
NULL
,
Gpr15
,
4
),
REG
(
NULL
,
"r16"
,
NULL
,
Gpr16
,
4
),
REG
(
NULL
,
"r17"
,
NULL
,
Gpr17
,
4
),
REG
(
NULL
,
"r18"
,
NULL
,
Gpr18
,
4
),
REG
(
NULL
,
"r19"
,
NULL
,
Gpr19
,
4
),
REG
(
NULL
,
"r20"
,
NULL
,
Gpr20
,
4
),
REG
(
NULL
,
"r21"
,
NULL
,
Gpr21
,
4
),
REG
(
NULL
,
"r22"
,
NULL
,
Gpr22
,
4
),
REG
(
NULL
,
"r23"
,
NULL
,
Gpr23
,
4
),
REG
(
NULL
,
"r24"
,
NULL
,
Gpr24
,
4
),
REG
(
NULL
,
"r25"
,
NULL
,
Gpr25
,
4
),
REG
(
NULL
,
"r26"
,
NULL
,
Gpr26
,
4
),
REG
(
NULL
,
"r27"
,
NULL
,
Gpr27
,
4
),
REG
(
NULL
,
"r28"
,
NULL
,
Gpr28
,
4
),
REG
(
NULL
,
"r29"
,
NULL
,
Gpr29
,
4
),
REG
(
NULL
,
"r30"
,
NULL
,
Gpr30
,
4
),
REG
(
NULL
,
"r31"
,
NULL
,
Gpr31
,
4
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Iar
,
4
),
REG
(
NULL
,
"msr"
,
NULL
,
Msr
,
4
),
REG
(
NULL
,
"cr"
,
NULL
,
Cr
,
4
),
REG
(
NULL
,
"lr"
,
"code_ptr"
,
Lr
,
4
),
REG
(
NULL
,
"ctr"
,
NULL
,
Ctr
,
4
),
REG
(
NULL
,
"xer"
,
NULL
,
Xer
,
4
),
REG
(
"fpu"
,
"f0"
,
Fpr0
,
4
),
REG
(
NULL
,
"f1"
,
Fpr1
,
4
),
REG
(
NULL
,
"f2"
,
Fpr2
,
4
),
REG
(
NULL
,
"f3"
,
Fpr3
,
4
),
REG
(
NULL
,
"f4"
,
Fpr4
,
4
),
REG
(
NULL
,
"f5"
,
Fpr5
,
4
),
REG
(
NULL
,
"f6"
,
Fpr6
,
4
),
REG
(
NULL
,
"f7"
,
Fpr7
,
4
),
REG
(
NULL
,
"f8"
,
Fpr8
,
4
),
REG
(
NULL
,
"f9"
,
Fpr9
,
4
),
REG
(
NULL
,
"f10"
,
Fpr10
,
4
),
REG
(
NULL
,
"f11"
,
Fpr11
,
4
),
REG
(
NULL
,
"f12"
,
Fpr12
,
4
),
REG
(
NULL
,
"f13"
,
Fpr13
,
4
),
REG
(
NULL
,
"f14"
,
Fpr14
,
4
),
REG
(
NULL
,
"f15"
,
Fpr15
,
4
),
REG
(
NULL
,
"f16"
,
Fpr16
,
4
),
REG
(
NULL
,
"f17"
,
Fpr17
,
4
),
REG
(
NULL
,
"f18"
,
Fpr18
,
4
),
REG
(
NULL
,
"f19"
,
Fpr19
,
4
),
REG
(
NULL
,
"f20"
,
Fpr20
,
4
),
REG
(
NULL
,
"f21"
,
Fpr21
,
4
),
REG
(
NULL
,
"f22"
,
Fpr22
,
4
),
REG
(
NULL
,
"f23"
,
Fpr23
,
4
),
REG
(
NULL
,
"f24"
,
Fpr24
,
4
),
REG
(
NULL
,
"f25"
,
Fpr25
,
4
),
REG
(
NULL
,
"f26"
,
Fpr26
,
4
),
REG
(
NULL
,
"f27"
,
Fpr27
,
4
),
REG
(
NULL
,
"f28"
,
Fpr28
,
4
),
REG
(
NULL
,
"f29"
,
Fpr29
,
4
),
REG
(
NULL
,
"f30"
,
Fpr30
,
4
),
REG
(
NULL
,
"f31"
,
Fpr31
,
4
),
REG
(
NULL
,
"fpscr"
,
Fpscr
,
4
),
REG
(
"core"
,
"r0"
,
NULL
,
Gpr0
),
REG
(
NULL
,
"r1"
,
NULL
,
Gpr1
),
REG
(
NULL
,
"r2"
,
NULL
,
Gpr2
),
REG
(
NULL
,
"r3"
,
NULL
,
Gpr3
),
REG
(
NULL
,
"r4"
,
NULL
,
Gpr4
),
REG
(
NULL
,
"r5"
,
NULL
,
Gpr5
),
REG
(
NULL
,
"r6"
,
NULL
,
Gpr6
),
REG
(
NULL
,
"r7"
,
NULL
,
Gpr7
),
REG
(
NULL
,
"r8"
,
NULL
,
Gpr8
),
REG
(
NULL
,
"r9"
,
NULL
,
Gpr9
),
REG
(
NULL
,
"r10"
,
NULL
,
Gpr10
),
REG
(
NULL
,
"r11"
,
NULL
,
Gpr11
),
REG
(
NULL
,
"r12"
,
NULL
,
Gpr12
),
REG
(
NULL
,
"r13"
,
NULL
,
Gpr13
),
REG
(
NULL
,
"r14"
,
NULL
,
Gpr14
),
REG
(
NULL
,
"r15"
,
NULL
,
Gpr15
),
REG
(
NULL
,
"r16"
,
NULL
,
Gpr16
),
REG
(
NULL
,
"r17"
,
NULL
,
Gpr17
),
REG
(
NULL
,
"r18"
,
NULL
,
Gpr18
),
REG
(
NULL
,
"r19"
,
NULL
,
Gpr19
),
REG
(
NULL
,
"r20"
,
NULL
,
Gpr20
),
REG
(
NULL
,
"r21"
,
NULL
,
Gpr21
),
REG
(
NULL
,
"r22"
,
NULL
,
Gpr22
),
REG
(
NULL
,
"r23"
,
NULL
,
Gpr23
),
REG
(
NULL
,
"r24"
,
NULL
,
Gpr24
),
REG
(
NULL
,
"r25"
,
NULL
,
Gpr25
),
REG
(
NULL
,
"r26"
,
NULL
,
Gpr26
),
REG
(
NULL
,
"r27"
,
NULL
,
Gpr27
),
REG
(
NULL
,
"r28"
,
NULL
,
Gpr28
),
REG
(
NULL
,
"r29"
,
NULL
,
Gpr29
),
REG
(
NULL
,
"r30"
,
NULL
,
Gpr30
),
REG
(
NULL
,
"r31"
,
NULL
,
Gpr31
),
REG
(
NULL
,
"pc"
,
"code_ptr"
,
Iar
),
REG
(
NULL
,
"msr"
,
NULL
,
Msr
),
REG
(
NULL
,
"cr"
,
NULL
,
Cr
),
REG
(
NULL
,
"lr"
,
"code_ptr"
,
Lr
),
REG
(
NULL
,
"ctr"
,
NULL
,
Ctr
),
REG
(
NULL
,
"xer"
,
NULL
,
Xer
),
REG
(
"fpu"
,
"f0"
,
"ieee_single"
,
Fpr0
,
4
),
REG
(
NULL
,
"f1"
,
"ieee_single"
,
Fpr1
,
4
),
REG
(
NULL
,
"f2"
,
"ieee_single"
,
Fpr2
,
4
),
REG
(
NULL
,
"f3"
,
"ieee_single"
,
Fpr3
,
4
),
REG
(
NULL
,
"f4"
,
"ieee_single"
,
Fpr4
,
4
),
REG
(
NULL
,
"f5"
,
"ieee_single"
,
Fpr5
,
4
),
REG
(
NULL
,
"f6"
,
"ieee_single"
,
Fpr6
,
4
),
REG
(
NULL
,
"f7"
,
"ieee_single"
,
Fpr7
,
4
),
REG
(
NULL
,
"f8"
,
"ieee_single"
,
Fpr8
,
4
),
REG
(
NULL
,
"f9"
,
"ieee_single"
,
Fpr9
,
4
),
REG
(
NULL
,
"f10"
,
"ieee_single"
,
Fpr10
,
4
),
REG
(
NULL
,
"f11"
,
"ieee_single"
,
Fpr11
,
4
),
REG
(
NULL
,
"f12"
,
"ieee_single"
,
Fpr12
,
4
),
REG
(
NULL
,
"f13"
,
"ieee_single"
,
Fpr13
,
4
),
REG
(
NULL
,
"f14"
,
"ieee_single"
,
Fpr14
,
4
),
REG
(
NULL
,
"f15"
,
"ieee_single"
,
Fpr15
,
4
),
REG
(
NULL
,
"f16"
,
"ieee_single"
,
Fpr16
,
4
),
REG
(
NULL
,
"f17"
,
"ieee_single"
,
Fpr17
,
4
),
REG
(
NULL
,
"f18"
,
"ieee_single"
,
Fpr18
,
4
),
REG
(
NULL
,
"f19"
,
"ieee_single"
,
Fpr19
,
4
),
REG
(
NULL
,
"f20"
,
"ieee_single"
,
Fpr20
,
4
),
REG
(
NULL
,
"f21"
,
"ieee_single"
,
Fpr21
,
4
),
REG
(
NULL
,
"f22"
,
"ieee_single"
,
Fpr22
,
4
),
REG
(
NULL
,
"f23"
,
"ieee_single"
,
Fpr23
,
4
),
REG
(
NULL
,
"f24"
,
"ieee_single"
,
Fpr24
,
4
),
REG
(
NULL
,
"f25"
,
"ieee_single"
,
Fpr25
,
4
),
REG
(
NULL
,
"f26"
,
"ieee_single"
,
Fpr26
,
4
),
REG
(
NULL
,
"f27"
,
"ieee_single"
,
Fpr27
,
4
),
REG
(
NULL
,
"f28"
,
"ieee_single"
,
Fpr28
,
4
),
REG
(
NULL
,
"f29"
,
"ieee_single"
,
Fpr29
,
4
),
REG
(
NULL
,
"f30"
,
"ieee_single"
,
Fpr30
,
4
),
REG
(
NULL
,
"f31"
,
"ieee_single"
,
Fpr31
,
4
),
REG
(
NULL
,
"fpscr"
,
NULL
,
Fpscr
,
4
),
/* FIXME: MQ is missing? FIELD_OFFSET(CONTEXT, Mq), */
/* see gdb/nlm/ppc.c */
...
...
programs/winedbg/be_x86_64.c
View file @
fd6ea955
...
...
@@ -768,67 +768,67 @@ static BOOL be_x86_64_set_context(HANDLE thread, const dbg_ctx_t *ctx)
return
SetThreadContext
(
thread
,
&
ctx
->
ctx
);
}
#define REG(f,n,t,r
,gs) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r), gs
}
#define REG(f,n,t,r
) {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r)
}
static
struct
gdb_register
be_x86_64_gdb_register_map
[]
=
{
REG
(
"core"
,
"rax"
,
NULL
,
Rax
,
8
),
REG
(
NULL
,
"rbx"
,
NULL
,
Rbx
,
8
),
REG
(
NULL
,
"rcx"
,
NULL
,
Rcx
,
8
),
REG
(
NULL
,
"rdx"
,
NULL
,
Rdx
,
8
),
REG
(
NULL
,
"rsi"
,
NULL
,
Rsi
,
8
),
REG
(
NULL
,
"rdi"
,
NULL
,
Rdi
,
8
),
REG
(
NULL
,
"rbp"
,
"data_ptr"
,
Rbp
,
8
),
REG
(
NULL
,
"rsp"
,
"data_ptr"
,
Rsp
,
8
),
REG
(
NULL
,
"r8"
,
NULL
,
R8
,
8
),
REG
(
NULL
,
"r9"
,
NULL
,
R9
,
8
),
REG
(
NULL
,
"r10"
,
NULL
,
R10
,
8
),
REG
(
NULL
,
"r11"
,
NULL
,
R11
,
8
),
REG
(
NULL
,
"r12"
,
NULL
,
R12
,
8
),
REG
(
NULL
,
"r13"
,
NULL
,
R13
,
8
),
REG
(
NULL
,
"r14"
,
NULL
,
R14
,
8
),
REG
(
NULL
,
"r15"
,
NULL
,
R15
,
8
),
REG
(
NULL
,
"rip"
,
"code_ptr"
,
Rip
,
8
),
REG
(
NULL
,
"eflags"
,
"i386_eflags"
,
EFlags
,
4
),
REG
(
NULL
,
"cs"
,
NULL
,
SegCs
,
4
),
REG
(
NULL
,
"ss"
,
NULL
,
SegSs
,
4
),
REG
(
NULL
,
"ds"
,
NULL
,
SegDs
,
4
),
REG
(
NULL
,
"es"
,
NULL
,
SegEs
,
4
),
REG
(
NULL
,
"fs"
,
NULL
,
SegFs
,
4
),
REG
(
NULL
,
"gs"
,
NULL
,
SegGs
,
4
),
{
NULL
,
"st0"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
0
]),
10
,
10
},
{
NULL
,
"st1"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
1
]),
10
,
10
},
{
NULL
,
"st2"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
2
]),
10
,
10
},
{
NULL
,
"st3"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
3
]),
10
,
10
},
{
NULL
,
"st4"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
4
]),
10
,
10
},
{
NULL
,
"st5"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
5
]),
10
,
10
},
{
NULL
,
"st6"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
6
]),
10
,
10
},
{
NULL
,
"st7"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
7
]),
10
,
10
},
REG
(
NULL
,
"fctrl"
,
NULL
,
u
.
FltSave
.
ControlWord
,
4
),
REG
(
NULL
,
"fstat"
,
NULL
,
u
.
FltSave
.
StatusWord
,
4
),
REG
(
NULL
,
"ftag"
,
NULL
,
u
.
FltSave
.
TagWord
,
4
),
REG
(
NULL
,
"fiseg"
,
NULL
,
u
.
FltSave
.
ErrorSelector
,
4
),
REG
(
NULL
,
"fioff"
,
NULL
,
u
.
FltSave
.
ErrorOffset
,
4
),
REG
(
NULL
,
"foseg"
,
NULL
,
u
.
FltSave
.
DataSelector
,
4
),
REG
(
NULL
,
"fooff"
,
NULL
,
u
.
FltSave
.
DataOffset
,
4
),
REG
(
NULL
,
"fop"
,
NULL
,
u
.
FltSave
.
ErrorOpcode
,
4
),
REG
(
"sse"
,
"xmm0"
,
"vec128"
,
u
.
s
.
Xmm0
,
16
),
REG
(
NULL
,
"xmm1"
,
"vec128"
,
u
.
s
.
Xmm1
,
16
),
REG
(
NULL
,
"xmm2"
,
"vec128"
,
u
.
s
.
Xmm2
,
16
),
REG
(
NULL
,
"xmm3"
,
"vec128"
,
u
.
s
.
Xmm3
,
16
),
REG
(
NULL
,
"xmm4"
,
"vec128"
,
u
.
s
.
Xmm4
,
16
),
REG
(
NULL
,
"xmm5"
,
"vec128"
,
u
.
s
.
Xmm5
,
16
),
REG
(
NULL
,
"xmm6"
,
"vec128"
,
u
.
s
.
Xmm6
,
16
),
REG
(
NULL
,
"xmm7"
,
"vec128"
,
u
.
s
.
Xmm7
,
16
),
REG
(
NULL
,
"xmm8"
,
"vec128"
,
u
.
s
.
Xmm8
,
16
),
REG
(
NULL
,
"xmm9"
,
"vec128"
,
u
.
s
.
Xmm9
,
16
),
REG
(
NULL
,
"xmm10"
,
"vec128"
,
u
.
s
.
Xmm10
,
16
),
REG
(
NULL
,
"xmm11"
,
"vec128"
,
u
.
s
.
Xmm11
,
16
),
REG
(
NULL
,
"xmm12"
,
"vec128"
,
u
.
s
.
Xmm12
,
16
),
REG
(
NULL
,
"xmm13"
,
"vec128"
,
u
.
s
.
Xmm13
,
16
),
REG
(
NULL
,
"xmm14"
,
"vec128"
,
u
.
s
.
Xmm14
,
16
),
REG
(
NULL
,
"xmm15"
,
"vec128"
,
u
.
s
.
Xmm15
,
16
),
REG
(
NULL
,
"mxcsr"
,
"i386_mxcsr"
,
u
.
FltSave
.
MxCsr
,
4
),
REG
(
"core"
,
"rax"
,
NULL
,
Rax
),
REG
(
NULL
,
"rbx"
,
NULL
,
Rbx
),
REG
(
NULL
,
"rcx"
,
NULL
,
Rcx
),
REG
(
NULL
,
"rdx"
,
NULL
,
Rdx
),
REG
(
NULL
,
"rsi"
,
NULL
,
Rsi
),
REG
(
NULL
,
"rdi"
,
NULL
,
Rdi
),
REG
(
NULL
,
"rbp"
,
"data_ptr"
,
Rbp
),
REG
(
NULL
,
"rsp"
,
"data_ptr"
,
Rsp
),
REG
(
NULL
,
"r8"
,
NULL
,
R8
),
REG
(
NULL
,
"r9"
,
NULL
,
R9
),
REG
(
NULL
,
"r10"
,
NULL
,
R10
),
REG
(
NULL
,
"r11"
,
NULL
,
R11
),
REG
(
NULL
,
"r12"
,
NULL
,
R12
),
REG
(
NULL
,
"r13"
,
NULL
,
R13
),
REG
(
NULL
,
"r14"
,
NULL
,
R14
),
REG
(
NULL
,
"r15"
,
NULL
,
R15
),
REG
(
NULL
,
"rip"
,
"code_ptr"
,
Rip
),
REG
(
NULL
,
"eflags"
,
"i386_eflags"
,
EFlags
),
REG
(
NULL
,
"cs"
,
NULL
,
SegCs
),
REG
(
NULL
,
"ss"
,
NULL
,
SegSs
),
REG
(
NULL
,
"ds"
,
NULL
,
SegDs
),
REG
(
NULL
,
"es"
,
NULL
,
SegEs
),
REG
(
NULL
,
"fs"
,
NULL
,
SegFs
),
REG
(
NULL
,
"gs"
,
NULL
,
SegGs
),
{
NULL
,
"st0"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
0
]),
10
},
{
NULL
,
"st1"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
1
]),
10
},
{
NULL
,
"st2"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
2
]),
10
},
{
NULL
,
"st3"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
3
]),
10
},
{
NULL
,
"st4"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
4
]),
10
},
{
NULL
,
"st5"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
5
]),
10
},
{
NULL
,
"st6"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
6
]),
10
},
{
NULL
,
"st7"
,
"i387_ext"
,
FIELD_OFFSET
(
CONTEXT
,
u
.
FltSave
.
FloatRegisters
[
7
]),
10
},
REG
(
NULL
,
"fctrl"
,
NULL
,
u
.
FltSave
.
ControlWord
),
REG
(
NULL
,
"fstat"
,
NULL
,
u
.
FltSave
.
StatusWord
),
REG
(
NULL
,
"ftag"
,
NULL
,
u
.
FltSave
.
TagWord
),
REG
(
NULL
,
"fiseg"
,
NULL
,
u
.
FltSave
.
ErrorSelector
),
REG
(
NULL
,
"fioff"
,
NULL
,
u
.
FltSave
.
ErrorOffset
),
REG
(
NULL
,
"foseg"
,
NULL
,
u
.
FltSave
.
DataSelector
),
REG
(
NULL
,
"fooff"
,
NULL
,
u
.
FltSave
.
DataOffset
),
REG
(
NULL
,
"fop"
,
NULL
,
u
.
FltSave
.
ErrorOpcode
),
REG
(
"sse"
,
"xmm0"
,
"vec128"
,
u
.
s
.
Xmm0
),
REG
(
NULL
,
"xmm1"
,
"vec128"
,
u
.
s
.
Xmm1
),
REG
(
NULL
,
"xmm2"
,
"vec128"
,
u
.
s
.
Xmm2
),
REG
(
NULL
,
"xmm3"
,
"vec128"
,
u
.
s
.
Xmm3
),
REG
(
NULL
,
"xmm4"
,
"vec128"
,
u
.
s
.
Xmm4
),
REG
(
NULL
,
"xmm5"
,
"vec128"
,
u
.
s
.
Xmm5
),
REG
(
NULL
,
"xmm6"
,
"vec128"
,
u
.
s
.
Xmm6
),
REG
(
NULL
,
"xmm7"
,
"vec128"
,
u
.
s
.
Xmm7
),
REG
(
NULL
,
"xmm8"
,
"vec128"
,
u
.
s
.
Xmm8
),
REG
(
NULL
,
"xmm9"
,
"vec128"
,
u
.
s
.
Xmm9
),
REG
(
NULL
,
"xmm10"
,
"vec128"
,
u
.
s
.
Xmm10
),
REG
(
NULL
,
"xmm11"
,
"vec128"
,
u
.
s
.
Xmm11
),
REG
(
NULL
,
"xmm12"
,
"vec128"
,
u
.
s
.
Xmm12
),
REG
(
NULL
,
"xmm13"
,
"vec128"
,
u
.
s
.
Xmm13
),
REG
(
NULL
,
"xmm14"
,
"vec128"
,
u
.
s
.
Xmm14
),
REG
(
NULL
,
"xmm15"
,
"vec128"
,
u
.
s
.
Xmm15
),
REG
(
NULL
,
"mxcsr"
,
"i386_mxcsr"
,
u
.
FltSave
.
MxCsr
),
};
struct
backend_cpu
be_x86_64
=
...
...
programs/winedbg/gdbproxy.c
View file @
fd6ea955
...
...
@@ -172,13 +172,13 @@ static inline void* cpu_register_ptr(struct gdb_context *gdbctx,
dbg_ctx_t
*
ctx
,
unsigned
idx
)
{
assert
(
idx
<
gdbctx
->
process
->
be_cpu
->
gdb_num_regs
);
return
(
char
*
)
ctx
+
gdbctx
->
process
->
be_cpu
->
gdb_register_map
[
idx
].
ctx_
offset
;
return
(
char
*
)
ctx
+
gdbctx
->
process
->
be_cpu
->
gdb_register_map
[
idx
].
offset
;
}
static
inline
DWORD64
cpu_register
(
struct
gdb_context
*
gdbctx
,
dbg_ctx_t
*
ctx
,
unsigned
idx
)
{
switch
(
gdbctx
->
process
->
be_cpu
->
gdb_register_map
[
idx
].
ctx_
length
)
switch
(
gdbctx
->
process
->
be_cpu
->
gdb_register_map
[
idx
].
length
)
{
case
1
:
return
*
(
BYTE
*
)
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
);
case
2
:
return
*
(
WORD
*
)
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
);
...
...
@@ -186,7 +186,7 @@ static inline DWORD64 cpu_register(struct gdb_context *gdbctx,
case
8
:
return
*
(
DWORD64
*
)
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
);
default:
ERR
(
"got unexpected size: %u
\n
"
,
(
unsigned
)
gdbctx
->
process
->
be_cpu
->
gdb_register_map
[
idx
].
ctx_
length
);
(
unsigned
)
gdbctx
->
process
->
be_cpu
->
gdb_register_map
[
idx
].
length
);
assert
(
0
);
return
0
;
}
...
...
@@ -196,30 +196,7 @@ static inline void cpu_register_hex_from(struct gdb_context *gdbctx,
dbg_ctx_t
*
ctx
,
unsigned
idx
,
const
char
**
phex
)
{
const
struct
gdb_register
*
cpu_register_map
=
gdbctx
->
process
->
be_cpu
->
gdb_register_map
;
if
(
cpu_register_map
[
idx
].
gdb_length
==
cpu_register_map
[
idx
].
ctx_length
)
hex_from
(
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
),
*
phex
,
cpu_register_map
[
idx
].
gdb_length
);
else
{
DWORD64
val
=
0
;
unsigned
i
;
BYTE
b
;
for
(
i
=
0
;
i
<
cpu_register_map
[
idx
].
gdb_length
;
i
++
)
{
hex_from
(
&
b
,
*
phex
,
1
);
*
phex
+=
2
;
val
+=
(
DWORD64
)
b
<<
(
8
*
i
);
}
switch
(
cpu_register_map
[
idx
].
ctx_length
)
{
case
1
:
*
(
BYTE
*
)
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
)
=
(
BYTE
)
val
;
break
;
case
2
:
*
(
WORD
*
)
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
)
=
(
WORD
)
val
;
break
;
case
4
:
*
(
DWORD
*
)
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
)
=
(
DWORD
)
val
;
break
;
case
8
:
*
(
DWORD64
*
)
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
)
=
val
;
break
;
default:
assert
(
0
);
}
}
hex_from
(
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
),
*
phex
,
cpu_register_map
[
idx
].
length
);
}
/* =============================================== *
...
...
@@ -790,22 +767,7 @@ static enum packet_return packet_reply_error(struct gdb_context* gdbctx, int err
static
inline
void
packet_reply_register_hex_to
(
struct
gdb_context
*
gdbctx
,
dbg_ctx_t
*
ctx
,
unsigned
idx
)
{
const
struct
gdb_register
*
cpu_register_map
=
gdbctx
->
process
->
be_cpu
->
gdb_register_map
;
if
(
cpu_register_map
[
idx
].
gdb_length
==
cpu_register_map
[
idx
].
ctx_length
)
packet_reply_hex_to
(
gdbctx
,
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
),
cpu_register_map
[
idx
].
gdb_length
);
else
{
DWORD64
val
=
cpu_register
(
gdbctx
,
ctx
,
idx
);
unsigned
i
;
for
(
i
=
0
;
i
<
cpu_register_map
[
idx
].
gdb_length
;
i
++
)
{
BYTE
b
=
val
;
packet_reply_hex_to
(
gdbctx
,
&
b
,
1
);
val
>>=
8
;
}
}
packet_reply_hex_to
(
gdbctx
,
cpu_register_ptr
(
gdbctx
,
ctx
,
idx
),
cpu_register_map
[
idx
].
length
);
}
/* =============================================== *
...
...
@@ -1608,7 +1570,7 @@ static void packet_query_target_xml(struct gdb_context* gdbctx, struct backend_c
}
snprintf
(
buffer
,
ARRAY_SIZE
(
buffer
),
"<reg name=
\"
%s
\"
bitsize=
\"
%zu
\"
"
,
cpu
->
gdb_register_map
[
i
].
name
,
8
*
cpu
->
gdb_register_map
[
i
].
gdb_
length
);
cpu
->
gdb_register_map
[
i
].
name
,
8
*
cpu
->
gdb_register_map
[
i
].
length
);
packet_reply_add
(
gdbctx
,
buffer
);
if
(
cpu
->
gdb_register_map
[
i
].
type
)
...
...
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