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Commit de1cb029 authored by Paul Gofman's avatar Paul Gofman Committed by Alexandre Julliard
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include: Define _XSAVE_FORMAT structure.

The structure is defined for both x86_64 and i386 (along with M128A) in (newer) Windows SDK. Signed-off-by: 's avatarPaul Gofman <pgofman@codeweavers.com> Signed-off-by: 's avatarAlexandre Julliard <julliard@winehq.org>
parent 25d4c50d
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Showing with 57 additions and 160 deletions
dlls/ntdll/signal_i386.c
View file @ de1cb029
......@@ -36,34 +36,6 @@
WINE_DEFAULT_DEBUG_CHANNEL(seh);
/* not defined for x86, so copy the x86_64 definition */
typedef struct DECLSPEC_ALIGN(16) _M128A
{
ULONGLONG Low;
LONGLONG High;
} M128A;
typedef struct
{
WORD ControlWord;
WORD StatusWord;
BYTE TagWord;
BYTE Reserved1;
WORD ErrorOpcode;
DWORD ErrorOffset;
WORD ErrorSelector;
WORD Reserved2;
DWORD DataOffset;
WORD DataSelector;
WORD Reserved3;
DWORD MxCsr;
DWORD MxCsr_Mask;
M128A FloatRegisters[8];
M128A XmmRegisters[16];
BYTE Reserved4[96];
} XMM_SAVE_AREA32;
struct x86_thread_data
{
DWORD fs; /* 1d4 TEB selector */
......@@ -287,8 +259,8 @@ static inline void save_fpux( CONTEXT *context )
{
#ifdef __GNUC__
/* we have to enforce alignment by hand */
char buffer[sizeof(XMM_SAVE_AREA32) + 16];
XMM_SAVE_AREA32 *state = (XMM_SAVE_AREA32 *)(((ULONG_PTR)buffer + 15) & ~15);
char buffer[sizeof(XSAVE_FORMAT) + 16];
XSAVE_FORMAT *state = (XSAVE_FORMAT *)(((ULONG_PTR)buffer + 15) & ~15);
context->ContextFlags |= CONTEXT_EXTENDED_REGISTERS;
__asm__ __volatile__( "fxsave %0" : "=m" (*state) );
......
dlls/ntdll/unix/signal_i386.c
View file @ de1cb029
......@@ -65,33 +65,6 @@ WINE_DEFAULT_DEBUG_CHANNEL(seh);
#undef ERR /* Solaris needs to define this */
/* not defined for x86, so copy the x86_64 definition */
typedef struct DECLSPEC_ALIGN(16) _M128A
{
ULONGLONG Low;
LONGLONG High;
} M128A;
typedef struct
{
WORD ControlWord;
WORD StatusWord;
BYTE TagWord;
BYTE Reserved1;
WORD ErrorOpcode;
DWORD ErrorOffset;
WORD ErrorSelector;
WORD Reserved2;
DWORD DataOffset;
WORD DataSelector;
WORD Reserved3;
DWORD MxCsr;
DWORD MxCsr_Mask;
M128A FloatRegisters[8];
M128A XmmRegisters[16];
BYTE Reserved4[96];
} XMM_SAVE_AREA32;
/***********************************************************************
* signal context platform-specific definitions
*/
......@@ -171,7 +144,7 @@ typedef struct ucontext
#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
#define FPU_sig(context) ((FLOATING_SAVE_AREA*)((context)->uc_mcontext.fpregs))
#define FPUX_sig(context) (FPU_sig(context) && !((context)->uc_mcontext.fpregs->status >> 16) ? (XMM_SAVE_AREA32 *)(FPU_sig(context) + 1) : NULL)
#define FPUX_sig(context) (FPU_sig(context) && !((context)->uc_mcontext.fpregs->status >> 16) ? (XSAVE_FORMAT *)(FPU_sig(context) + 1) : NULL)
#ifdef __ANDROID__
/* custom signal restorer since we may have unmapped the one in vdso, and bionic doesn't check for that */
......@@ -336,7 +309,7 @@ static inline int set_thread_area( struct modify_ldt_s *ptr )
#define TRAP_sig(context) ((context)->uc_mcontext->__es.__trapno)
#define ERROR_sig(context) ((context)->uc_mcontext->__es.__err)
#define FPU_sig(context) NULL
#define FPUX_sig(context) ((XMM_SAVE_AREA32 *)&(context)->uc_mcontext->__fs.__fpu_fcw)
#define FPUX_sig(context) ((XSAVE_FORMAT *)&(context)->uc_mcontext->__fs.__fpu_fcw)
#else
#define EAX_sig(context) ((context)->uc_mcontext->ss.eax)
#define EBX_sig(context) ((context)->uc_mcontext->ss.ebx)
......@@ -357,7 +330,7 @@ static inline int set_thread_area( struct modify_ldt_s *ptr )
#define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
#define ERROR_sig(context) ((context)->uc_mcontext->es.err)
#define FPU_sig(context) NULL
#define FPUX_sig(context) ((XMM_SAVE_AREA32 *)&(context)->uc_mcontext->fs.fpu_fcw)
#define FPUX_sig(context) ((XSAVE_FORMAT *)&(context)->uc_mcontext->fs.fpu_fcw)
#endif
#elif defined(__NetBSD__)
......@@ -387,7 +360,7 @@ static inline int set_thread_area( struct modify_ldt_s *ptr )
#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
#define FPU_sig(context) NULL
#define FPUX_sig(context) ((XMM_SAVE_AREA32 *)&((context)->uc_mcontext.__fpregs))
#define FPUX_sig(context) ((XSAVE_FORMAT *)&((context)->uc_mcontext.__fpregs))
#define T_MCHK T_MCA
#define T_XMMFLT T_XMM
......@@ -687,8 +660,8 @@ static inline void save_fpu( CONTEXT *context )
static inline void save_fpux( CONTEXT *context )
{
/* we have to enforce alignment by hand */
char buffer[sizeof(XMM_SAVE_AREA32) + 16];
XMM_SAVE_AREA32 *state = (XMM_SAVE_AREA32 *)(((ULONG_PTR)buffer + 15) & ~15);
char buffer[sizeof(XSAVE_FORMAT) + 16];
XSAVE_FORMAT *state = (XSAVE_FORMAT *)(((ULONG_PTR)buffer + 15) & ~15);
context->ContextFlags |= CONTEXT_EXTENDED_REGISTERS;
__asm__ __volatile__( "fxsave %0" : "=m" (*state) );
......@@ -718,8 +691,8 @@ static inline void restore_fpu( const CONTEXT *context )
static inline void restore_fpux( const CONTEXT *context )
{
/* we have to enforce alignment by hand */
char buffer[sizeof(XMM_SAVE_AREA32) + 16];
XMM_SAVE_AREA32 *state = (XMM_SAVE_AREA32 *)(((ULONG_PTR)buffer + 15) & ~15);
char buffer[sizeof(XSAVE_FORMAT) + 16];
XSAVE_FORMAT *state = (XSAVE_FORMAT *)(((ULONG_PTR)buffer + 15) & ~15);
memcpy( state, context->ExtendedRegisters, sizeof(*state) );
/* reset the current interrupt status */
......@@ -733,7 +706,7 @@ static inline void restore_fpux( const CONTEXT *context )
*
* Build a standard FPU context from an extended one.
*/
static void fpux_to_fpu( FLOATING_SAVE_AREA *fpu, const XMM_SAVE_AREA32 *fpux )
static void fpux_to_fpu( FLOATING_SAVE_AREA *fpu, const XSAVE_FORMAT *fpux )
{
unsigned int i, tag, stack_top;
......@@ -782,7 +755,7 @@ static void fpux_to_fpu( FLOATING_SAVE_AREA *fpu, const XMM_SAVE_AREA32 *fpux )
static inline void save_context( CONTEXT *context, const ucontext_t *sigcontext )
{
FLOATING_SAVE_AREA *fpu = FPU_sig(sigcontext);
XMM_SAVE_AREA32 *fpux = FPUX_sig(sigcontext);
XSAVE_FORMAT *fpux = FPUX_sig(sigcontext);
memset(context, 0, sizeof(*context));
context->ContextFlags = CONTEXT_FULL | CONTEXT_DEBUG_REGISTERS;
......@@ -832,7 +805,7 @@ static inline void save_context( CONTEXT *context, const ucontext_t *sigcontext
static inline void restore_context( const CONTEXT *context, ucontext_t *sigcontext )
{
FLOATING_SAVE_AREA *fpu = FPU_sig(sigcontext);
XMM_SAVE_AREA32 *fpux = FPUX_sig(sigcontext);
XSAVE_FORMAT *fpux = FPUX_sig(sigcontext);
x86_thread_data()->dr0 = context->Dr0;
x86_thread_data()->dr1 = context->Dr1;
......@@ -2260,8 +2233,8 @@ static void init_thread_context( CONTEXT *context, LPTHREAD_START_ROUTINE entry,
context->Esp = (DWORD)NtCurrentTeb()->Tib.StackBase - 16;
context->Eip = (DWORD)relay;
context->FloatSave.ControlWord = 0x27f;
((XMM_SAVE_AREA32 *)context->ExtendedRegisters)->ControlWord = 0x27f;
((XMM_SAVE_AREA32 *)context->ExtendedRegisters)->MxCsr = 0x1f80;
((XSAVE_FORMAT *)context->ExtendedRegisters)->ControlWord = 0x27f;
((XSAVE_FORMAT *)context->ExtendedRegisters)->MxCsr = 0x1f80;
}
......
dlls/ntdll/unix/system.c
View file @ de1cb029
......@@ -240,33 +240,9 @@ static int have_cpuid(void)
static inline BOOL have_sse_daz_mode(void)
{
#ifdef __i386__
typedef struct DECLSPEC_ALIGN(16) _M128A {
ULONGLONG Low;
LONGLONG High;
} M128A;
typedef struct _XMM_SAVE_AREA32 {
WORD ControlWord;
WORD StatusWord;
BYTE TagWord;
BYTE Reserved1;
WORD ErrorOpcode;
DWORD ErrorOffset;
WORD ErrorSelector;
WORD Reserved2;
DWORD DataOffset;
WORD DataSelector;
WORD Reserved3;
DWORD MxCsr;
DWORD MxCsr_Mask;
M128A FloatRegisters[8];
M128A XmmRegisters[16];
BYTE Reserved4[96];
} XMM_SAVE_AREA32;
/* Intel says we need a zeroed 16-byte aligned buffer */
char buffer[512 + 16];
XMM_SAVE_AREA32 *state = (XMM_SAVE_AREA32 *)(((ULONG_PTR)buffer + 15) & ~15);
XSAVE_FORMAT *state = (XSAVE_FORMAT *)(((ULONG_PTR)buffer + 15) & ~15);
memset(buffer, 0, sizeof(buffer));
__asm__ __volatile__( "fxsave %0" : "=m" (*state) : "m" (*state) );
......
include/winnt.h
View file @ de1cb029
......@@ -1060,30 +1060,12 @@ typedef struct _LDT_ENTRY {
} HighWord;
} LDT_ENTRY, *PLDT_ENTRY, WOW64_LDT_ENTRY, *PWOW64_LDT_ENTRY;
/* x86-64 context definitions */
#if defined(__x86_64__)
#define CONTEXT_AMD64 0x00100000
#define CONTEXT_CONTROL (CONTEXT_AMD64 | 0x0001)
#define CONTEXT_INTEGER (CONTEXT_AMD64 | 0x0002)
#define CONTEXT_SEGMENTS (CONTEXT_AMD64 | 0x0004)
#define CONTEXT_FLOATING_POINT (CONTEXT_AMD64 | 0x0008)
#define CONTEXT_DEBUG_REGISTERS (CONTEXT_AMD64 | 0x0010)
#define CONTEXT_XSTATE (CONTEXT_AMD64 | 0x0040)
#define CONTEXT_FULL (CONTEXT_CONTROL | CONTEXT_INTEGER | CONTEXT_FLOATING_POINT)
#define CONTEXT_ALL (CONTEXT_CONTROL | CONTEXT_INTEGER | CONTEXT_SEGMENTS | CONTEXT_FLOATING_POINT | CONTEXT_DEBUG_REGISTERS)
#define EXCEPTION_READ_FAULT 0
#define EXCEPTION_WRITE_FAULT 1
#define EXCEPTION_EXECUTE_FAULT 8
typedef struct DECLSPEC_ALIGN(16) _M128A {
ULONGLONG Low;
LONGLONG High;
} M128A, *PM128A;
typedef struct _XMM_SAVE_AREA32 {
typedef struct _XSAVE_FORMAT {
WORD ControlWord; /* 000 */
WORD StatusWord; /* 002 */
BYTE TagWord; /* 004 */
......@@ -1100,7 +1082,27 @@ typedef struct _XMM_SAVE_AREA32 {
M128A FloatRegisters[8]; /* 020 */
M128A XmmRegisters[16]; /* 0a0 */
BYTE Reserved4[96]; /* 1a0 */
} XMM_SAVE_AREA32, *PXMM_SAVE_AREA32;
} XSAVE_FORMAT, *PXSAVE_FORMAT;
/* x86-64 context definitions */
#if defined(__x86_64__)
#define CONTEXT_AMD64 0x00100000
#define CONTEXT_CONTROL (CONTEXT_AMD64 | 0x0001)
#define CONTEXT_INTEGER (CONTEXT_AMD64 | 0x0002)
#define CONTEXT_SEGMENTS (CONTEXT_AMD64 | 0x0004)
#define CONTEXT_FLOATING_POINT (CONTEXT_AMD64 | 0x0008)
#define CONTEXT_DEBUG_REGISTERS (CONTEXT_AMD64 | 0x0010)
#define CONTEXT_XSTATE (CONTEXT_AMD64 | 0x0040)
#define CONTEXT_FULL (CONTEXT_CONTROL | CONTEXT_INTEGER | CONTEXT_FLOATING_POINT)
#define CONTEXT_ALL (CONTEXT_CONTROL | CONTEXT_INTEGER | CONTEXT_SEGMENTS | CONTEXT_FLOATING_POINT | CONTEXT_DEBUG_REGISTERS)
#define EXCEPTION_READ_FAULT 0
#define EXCEPTION_WRITE_FAULT 1
#define EXCEPTION_EXECUTE_FAULT 8
typedef XSAVE_FORMAT XMM_SAVE_AREA32, *PXMM_SAVE_AREA32;
typedef struct DECLSPEC_ALIGN(16) _CONTEXT {
DWORD64 P1Home; /* 000 */
......
programs/winedbg/be_i386.c
View file @ de1cb029
......@@ -33,32 +33,6 @@ extern void be_i386_disasm_one_insn(ADDRESS64* addr, int display);
#define IS_VM86_MODE(ctx) (ctx->EFlags & V86_FLAG)
#ifndef __x86_64__
typedef struct DECLSPEC_ALIGN(16) _M128A {
ULONGLONG Low;
LONGLONG High;
} M128A, *PM128A;
typedef struct _XMM_SAVE_AREA32 {
WORD ControlWord; /* 000 */
WORD StatusWord; /* 002 */
BYTE TagWord; /* 004 */
BYTE Reserved1; /* 005 */
WORD ErrorOpcode; /* 006 */
DWORD ErrorOffset; /* 008 */
WORD ErrorSelector; /* 00c */
WORD Reserved2; /* 00e */
DWORD DataOffset; /* 010 */
WORD DataSelector; /* 014 */
WORD Reserved3; /* 016 */
DWORD MxCsr; /* 018 */
DWORD MxCsr_Mask; /* 01c */
M128A FloatRegisters[8]; /* 020 */
M128A XmmRegisters[16]; /* 0a0 */
BYTE Reserved4[96]; /* 1a0 */
} XMM_SAVE_AREA32, *PXMM_SAVE_AREA32;
#endif
static ADDRESS_MODE get_selector_type(HANDLE hThread, const WOW64_CONTEXT *ctx, WORD sel)
{
LDT_ENTRY le;
......@@ -158,7 +132,7 @@ static void be_i386_all_print_context(HANDLE hThread, const dbg_ctx_t *pctx)
static const char mxcsr_flags[16][4] = { "IE", "DE", "ZE", "OE", "UE", "PE", "DAZ", "IM",
"DM", "ZM", "OM", "UM", "PM", "R-", "R+", "FZ" };
const WOW64_CONTEXT *ctx = &pctx->x86;
XMM_SAVE_AREA32 *xmm_area;
XSAVE_FORMAT *xmm_area;
long double ST[8]; /* These are for floating regs */
int cnt;
......@@ -223,7 +197,7 @@ static void be_i386_all_print_context(HANDLE hThread, const dbg_ctx_t *pctx)
dbg_printf(" ST%d:%Lf ", cnt, ST[cnt]);
}
xmm_area = (XMM_SAVE_AREA32 *) &ctx->ExtendedRegisters;
xmm_area = (XSAVE_FORMAT *) &ctx->ExtendedRegisters;
dbg_printf(" mxcsr: %04x (", xmm_area->MxCsr );
for (cnt = 0; cnt < 16; cnt++)
......@@ -350,14 +324,14 @@ static struct dbg_internal_var be_i386_ctx[] =
{CV_REG_ST0+5, "ST5", (DWORD_PTR*)FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[50]), dbg_itype_long_real},
{CV_REG_ST0+6, "ST6", (DWORD_PTR*)FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[60]), dbg_itype_long_real},
{CV_REG_ST0+7, "ST7", (DWORD_PTR*)FIELD_OFFSET(WOW64_CONTEXT, FloatSave.RegisterArea[70]), dbg_itype_long_real},
{CV_AMD64_XMM0, "XMM0", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[0])), dbg_itype_m128a},
{CV_AMD64_XMM0+1, "XMM1", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[1])), dbg_itype_m128a},
{CV_AMD64_XMM0+2, "XMM2", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[2])), dbg_itype_m128a},
{CV_AMD64_XMM0+3, "XMM3", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[3])), dbg_itype_m128a},
{CV_AMD64_XMM0+4, "XMM4", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[4])), dbg_itype_m128a},
{CV_AMD64_XMM0+5, "XMM5", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[5])), dbg_itype_m128a},
{CV_AMD64_XMM0+6, "XMM6", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[6])), dbg_itype_m128a},
{CV_AMD64_XMM0+7, "XMM7", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[7])), dbg_itype_m128a},
{CV_AMD64_XMM0, "XMM0", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[0])), dbg_itype_m128a},
{CV_AMD64_XMM0+1, "XMM1", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[1])), dbg_itype_m128a},
{CV_AMD64_XMM0+2, "XMM2", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[2])), dbg_itype_m128a},
{CV_AMD64_XMM0+3, "XMM3", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[3])), dbg_itype_m128a},
{CV_AMD64_XMM0+4, "XMM4", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[4])), dbg_itype_m128a},
{CV_AMD64_XMM0+5, "XMM5", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[5])), dbg_itype_m128a},
{CV_AMD64_XMM0+6, "XMM6", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[6])), dbg_itype_m128a},
{CV_AMD64_XMM0+7, "XMM7", (DWORD_PTR*)(FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[7])), dbg_itype_m128a},
{0, NULL, 0, dbg_itype_none}
};
......@@ -901,15 +875,15 @@ static struct gdb_register be_i386_gdb_register_map[] = {
REG(NULL, "fooff", NULL, FloatSave.DataOffset),
{ NULL, "fop", NULL, FIELD_OFFSET(WOW64_CONTEXT, FloatSave.ErrorSelector)+2, 2},
{ "sse", "xmm0", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[0]), 16},
{ NULL, "xmm1", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[1]), 16},
{ NULL, "xmm2", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[2]), 16},
{ NULL, "xmm3", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[3]), 16},
{ NULL, "xmm4", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[4]), 16},
{ NULL, "xmm5", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[5]), 16},
{ NULL, "xmm6", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[6]), 16},
{ NULL, "xmm7", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, XmmRegisters[7]), 16},
{ NULL, "mxcsr", "i386_mxcsr", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XMM_SAVE_AREA32, MxCsr), 4},
{ "sse", "xmm0", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[0]), 16},
{ NULL, "xmm1", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[1]), 16},
{ NULL, "xmm2", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[2]), 16},
{ NULL, "xmm3", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[3]), 16},
{ NULL, "xmm4", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[4]), 16},
{ NULL, "xmm5", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[5]), 16},
{ NULL, "xmm6", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[6]), 16},
{ NULL, "xmm7", "vec128", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, XmmRegisters[7]), 16},
{ NULL, "mxcsr", "i386_mxcsr", FIELD_OFFSET(WOW64_CONTEXT, ExtendedRegisters) + FIELD_OFFSET(XSAVE_FORMAT, MxCsr), 4},
};
struct backend_cpu be_i386 =
......
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