be_arm.c 59.8 KB
Newer Older
1 2 3
/*
 * Debugger ARM specific functions
 *
4
 * Copyright 2010-2013 André Hentschel
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
 */

#include "debugger.h"

23
#if defined(__arm__) && !defined(__ARMEB__)
24

25 26 27 28 29 30 31 32 33 34 35 36 37 38
/*
 * Switch to disassemble Thumb code.
 */
static BOOL db_disasm_thumb = FALSE;

/*
 * Flag to indicate whether we need to display instruction,
 * or whether we just need to know the address of the next
 * instruction.
 */
static BOOL db_display = FALSE;

#define ARM_INSN_SIZE    4
#define THUMB_INSN_SIZE  2
39
#define THUMB2_INSN_SIZE 4
40 41 42 43 44 45

#define ROR32(n, r) (((n) >> (r)) | ((n) << (32 - (r))))

#define get_cond(ins)           tbl_cond[(ins >> 28) & 0x0f]
#define get_nibble(ins, num)    ((ins >> (num * 4)) & 0x0f)

46 47 48 49 50
static char const tbl_regs[][4] = {
    "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
    "fp", "ip", "sp", "lr", "pc", "cpsr"
};

51 52 53 54 55 56 57 58 59 60 61 62 63
static char const tbl_addrmode[][3] = {
    "da", "ia", "db", "ib"
};

static char const tbl_cond[][3] = {
    "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", ""
};

static char const tbl_dataops[][4] = {
    "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", "tst", "teq", "cmp", "cmn", "orr",
    "mov", "bic", "mvn"
};

64 65 66 67
static char const tbl_shifts[][4] = {
    "lsl", "lsr", "asr", "ror"
};

68
static char const tbl_hiops_t[][4] = {
69
    "add", "cmp", "mov", "bx"
70 71
};

72 73 74 75 76
static char const tbl_aluops_t[][4] = {
    "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", "tst", "neg", "cmp", "cmn", "orr",
    "mul", "bic", "mvn"
};

77
static char const tbl_immops_t[][4] = {
78 79 80 81 82
    "mov", "cmp", "add", "sub"
};

static char const tbl_sregops_t[][5] = {
    "strh", "ldsb", "ldrh", "ldsh"
83 84
};

85 86 87 88
static char const tbl_miscops_t2[][6] = {
    "rev", "rev16", "rbit", "revsh"
};

89 90 91 92
static char const tbl_width_t2[][2] = {
    "b", "h", "", "?"
};

93 94 95 96 97
static char const tbl_special_regs_t2[][12] = {
    "apsr", "iapsr", "eapsr", "xpsr", "rsvd", "ipsr", "epsr", "iepsr", "msp", "psp", "rsvd", "rsvd",
    "rsvd", "rsvd", "rsvd", "rsvd", "primask", "basepri", "basepri_max", "faultmask", "control"
};

98 99 100 101
static char const tbl_hints_t2[][6] = {
    "nop", "yield", "wfe", "wfi", "sev"
};

102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
static UINT db_get_inst(void* addr, int size)
{
    UINT result = 0;
    char buffer[4];

    if (dbg_read_memory(addr, buffer, size))
    {
        switch (size)
        {
        case 4:
            result = *(UINT*)buffer;
            break;
        case 2:
            result = *(WORD*)buffer;
            break;
        }
    }
    return result;
}

122 123 124 125 126 127 128 129 130 131 132
static void db_printsym(unsigned int addr)
{
    ADDRESS64   a;

    a.Mode   = AddrModeFlat;
    a.Offset = addr;

    print_address(&a, TRUE);
}

static UINT arm_disasm_branch(UINT inst, ADDRESS64 *addr)
133 134 135 136 137 138 139
{
    short link = (inst >> 24) & 0x01;
    int offset = (inst << 2) & 0x03ffffff;

    if (offset & 0x02000000) offset |= 0xfc000000;
    offset += 8;

140 141
    dbg_printf("\n\tb%s%s\t", link ? "l" : "", get_cond(inst));
    db_printsym(addr->Offset + offset);
142 143 144
    return 0;
}

145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173
static UINT arm_disasm_mul(UINT inst, ADDRESS64 *addr)
{
    short accu = (inst >> 21) & 0x01;
    short condcodes = (inst >> 20) & 0x01;

    if (accu)
        dbg_printf("\n\tmla%s%s\t%s, %s, %s, %s", get_cond(inst), condcodes ? "s" : "",
                   tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
                   tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 3)]);
    else
        dbg_printf("\n\tmul%s%s\t%s, %s, %s", get_cond(inst), condcodes ? "s" : "",
                   tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
                   tbl_regs[get_nibble(inst, 2)]);
    return 0;
}

static UINT arm_disasm_longmul(UINT inst, ADDRESS64 *addr)
{
    short sign = (inst >> 22) & 0x01;
    short accu = (inst >> 21) & 0x01;
    short condcodes = (inst >> 20) & 0x01;

    dbg_printf("\n\t%s%s%s%s\t%s, %s, %s, %s", sign ? "s" : "u", accu ? "mlal" : "mull",
               get_cond(inst), condcodes ? "s" : "",
               tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)],
               tbl_regs[get_nibble(inst, 0)], tbl_regs[get_nibble(inst, 2)]);
    return 0;
}

174 175 176 177 178 179 180 181 182 183
static UINT arm_disasm_swp(UINT inst, ADDRESS64 *addr)
{
    short byte = (inst >> 22) & 0x01;

    dbg_printf("\n\tswp%s%s\t%s, %s, [%s]", get_cond(inst), byte ? "b" : "",
               tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 0)],
               tbl_regs[get_nibble(inst, 4)]);
    return 0;
}

184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
static UINT arm_disasm_halfwordtrans(UINT inst, ADDRESS64 *addr)
{
    short halfword  = (inst >> 5)  & 0x01;
    short sign      = (inst >> 6)  & 0x01;
    short load      = (inst >> 20) & 0x01;
    short writeback = (inst >> 21) & 0x01;
    short immediate = (inst >> 22) & 0x01;
    short direction = (inst >> 23) & 0x01;
    short indexing  = (inst >> 24) & 0x01;
    short offset    = ((inst >> 4) & 0xf0) + (inst & 0x0f);

    dbg_printf("\n\t%s%s%s%s%s", load ? "ldr" : "str", sign ? "s" : "",
               halfword ? "h" : (sign ? "b" : ""), writeback ? "t" : "", get_cond(inst));
    dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
    if (indexing)
    {
        if (immediate)
201
            dbg_printf("[%s, #%s%d]", tbl_regs[get_nibble(inst, 4)], direction ? "" : "-", offset);
202 203 204 205 206 207
        else
            dbg_printf("[%s, %s]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
    }
    else
    {
        if (immediate)
208
            dbg_printf("[%s], #%s%d", tbl_regs[get_nibble(inst, 4)], direction ? "" : "-", offset);
209 210 211 212 213 214
        else
            dbg_printf("[%s], %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
    }
    return 0;
}

215 216 217 218 219 220
static UINT arm_disasm_branchxchg(UINT inst, ADDRESS64 *addr)
{
    dbg_printf("\n\tbx%s\t%s", get_cond(inst), tbl_regs[get_nibble(inst, 0)]);
    return 0;
}

221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262
static UINT arm_disasm_mrstrans(UINT inst, ADDRESS64 *addr)
{
    short src = (inst >> 22) & 0x01;

    dbg_printf("\n\tmrs%s\t%s, %s", get_cond(inst), tbl_regs[get_nibble(inst, 3)],
               src ? "spsr" : "cpsr");
    return 0;
}

static UINT arm_disasm_msrtrans(UINT inst, ADDRESS64 *addr)
{
    short immediate = (inst >> 25) & 0x01;
    short dst = (inst >> 22) & 0x01;
    short simple = (inst >> 16) & 0x01;

    if (simple || !immediate)
    {
        dbg_printf("\n\tmsr%s\t%s, %s", get_cond(inst), dst ? "spsr" : "cpsr",
                   tbl_regs[get_nibble(inst, 0)]);
        return 0;
    }

    dbg_printf("\n\tmsr%s\t%s, #%u", get_cond(inst), dst ? "spsr" : "cpsr",
               ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
    return 0;
}

static UINT arm_disasm_wordmov(UINT inst, ADDRESS64 *addr)
{
    short top = (inst >> 22) & 0x01;

    dbg_printf("\n\tmov%s%s\t%s, #%u", top ? "t" : "w", get_cond(inst),
               tbl_regs[get_nibble(inst, 3)], (get_nibble(inst, 4) << 12) | (inst & 0x0fff));
    return 0;
}

static UINT arm_disasm_nop(UINT inst, ADDRESS64 *addr)
{
    dbg_printf("\n\tnop%s", get_cond(inst));
    return 0;
}

263
static UINT arm_disasm_dataprocessing(UINT inst, ADDRESS64 *addr)
264 265 266 267 268
{
    short condcodes = (inst >> 20) & 0x01;
    short opcode    = (inst >> 21) & 0x0f;
    short immediate = (inst >> 25) & 0x01;
    short no_op1    = (opcode & 0x0d) == 0x0d;
269
    short no_dst    = (opcode & 0x0c) == 0x08;
270 271

    dbg_printf("\n\t%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond(inst));
272 273 274
    if (!no_dst) dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
    else dbg_printf("\t");

275 276 277
    if (no_op1)
    {
        if (immediate)
278
            dbg_printf("#%u", ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
279
        else
280
            dbg_printf("%s", tbl_regs[get_nibble(inst, 0)]);
281 282 283 284
    }
    else
    {
        if (immediate)
285
            dbg_printf("%s, #%u", tbl_regs[get_nibble(inst, 4)],
286
                       ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
287
        else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
288
            dbg_printf("%s, %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
289 290 291 292 293 294 295 296
        else if (((inst >> 4) & 0x09) == 0x01) /* register shift */
            dbg_printf("%s, %s, %s %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
                       tbl_shifts[(inst >> 5) & 0x03], tbl_regs[(inst >> 8) & 0x0f]);
        else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift */
            dbg_printf("%s, %s, %s #%d", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
                       tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
        else
            return inst;
297 298 299 300
    }
    return 0;
}

301
static UINT arm_disasm_singletrans(UINT inst, ADDRESS64 *addr)
302 303 304 305 306
{
    short load      = (inst >> 20) & 0x01;
    short writeback = (inst >> 21) & 0x01;
    short byte      = (inst >> 22) & 0x01;
    short direction = (inst >> 23) & 0x01;
307
    short indexing  = (inst >> 24) & 0x01;
308 309 310 311 312
    short immediate = !((inst >> 25) & 0x01);
    short offset    = inst & 0x0fff;

    dbg_printf("\n\t%s%s%s%s", load ? "ldr" : "str", byte ? "b" : "", writeback ? "t" : "",
               get_cond(inst));
313
    dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
314 315 316
    if (indexing)
    {
        if (immediate)
317
            dbg_printf("[%s, #%s%d]", tbl_regs[get_nibble(inst, 4)], direction ? "" : "-", offset);
318
        else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
319
            dbg_printf("[%s, %s]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
320 321 322 323 324
        else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift (there's no register shift) */
            dbg_printf("[%s, %s, %s #%d]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
                       tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
        else
            return inst;
325
    }
326
    else
327 328
    {
        if (immediate)
329
            dbg_printf("[%s], #%s%d", tbl_regs[get_nibble(inst, 4)], direction ? "" : "-", offset);
330
        else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
331
            dbg_printf("[%s], %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
332 333 334 335 336
        else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift (there's no register shift) */
            dbg_printf("[%s], %s, %s #%d", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
                       tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
        else
            return inst;
337
    }
338 339 340
    return 0;
}

341
static UINT arm_disasm_blocktrans(UINT inst, ADDRESS64 *addr)
342 343 344 345 346 347 348 349 350 351 352 353 354 355
{
    short load      = (inst >> 20) & 0x01;
    short writeback = (inst >> 21) & 0x01;
    short psr       = (inst >> 22) & 0x01;
    short addrmode  = (inst >> 23) & 0x03;
    short i;
    short last=15;
    for (i=15;i>=0;i--)
        if ((inst>>i) & 1)
        {
            last = i;
            break;
        }

356 357
    dbg_printf("\n\t%s%s%s\t%s%s, {", load ? "ldm" : "stm", tbl_addrmode[addrmode], get_cond(inst),
               tbl_regs[get_nibble(inst, 4)], writeback ? "!" : "");
358 359 360
    for (i=0;i<=15;i++)
        if ((inst>>i) & 1)
        {
361 362
            if (i == last) dbg_printf("%s", tbl_regs[i]);
            else dbg_printf("%s, ", tbl_regs[i]);
363 364 365 366 367
        }
    dbg_printf("}%s", psr ? "^" : "");
    return 0;
}

368
static UINT arm_disasm_swi(UINT inst, ADDRESS64 *addr)
369
{
370
    dbg_printf("\n\tswi%s\t#%d", get_cond(inst), inst & 0x00ffffff);
371 372 373
    return 0;
}

374
static UINT arm_disasm_coproctrans(UINT inst, ADDRESS64 *addr)
375 376 377 378 379 380 381 382
{
    WORD CRm    = inst & 0x0f;
    WORD CP     = (inst >> 5)  & 0x07;
    WORD CPnum  = (inst >> 8)  & 0x0f;
    WORD CRn    = (inst >> 16) & 0x0f;
    WORD load   = (inst >> 20) & 0x01;
    WORD CP_Opc = (inst >> 21) & 0x07;

383 384
    dbg_printf("\n\t%s%s\t%u, %u, %s, cr%u, cr%u, {%u}", load ? "mrc" : "mcr", get_cond(inst), CPnum,
               CP, tbl_regs[get_nibble(inst, 3)], CRn, CRm, CP_Opc);
385 386 387
    return 0;
}

388
static UINT arm_disasm_coprocdataop(UINT inst, ADDRESS64 *addr)
389 390 391 392 393 394 395 396 397 398 399 400 401
{
    WORD CRm    = inst & 0x0f;
    WORD CP     = (inst >> 5)  & 0x07;
    WORD CPnum  = (inst >> 8)  & 0x0f;
    WORD CRd    = (inst >> 12) & 0x0f;
    WORD CRn    = (inst >> 16) & 0x0f;
    WORD CP_Opc = (inst >> 20) & 0x0f;

    dbg_printf("\n\tcdp%s\t%u, %u, cr%u, cr%u, cr%u, {%u}", get_cond(inst),
               CPnum, CP, CRd, CRn, CRm, CP_Opc);
    return 0;
}

402
static UINT arm_disasm_coprocdatatrans(UINT inst, ADDRESS64 *addr)
403 404 405 406
{
    WORD CPnum  = (inst >> 8)  & 0x0f;
    WORD CRd    = (inst >> 12) & 0x0f;
    WORD load      = (inst >> 20) & 0x01;
407
    WORD writeback = (inst >> 21) & 0x01;
408 409
    WORD translen  = (inst >> 22) & 0x01;
    WORD direction = (inst >> 23) & 0x01;
410
    WORD indexing  = (inst >> 24) & 0x01;
411 412 413
    short offset    = (inst & 0xff) << 2;

    dbg_printf("\n\t%s%s%s", load ? "ldc" : "stc", translen ? "l" : "", get_cond(inst));
414
    if (indexing)
415
        dbg_printf("\t%u, cr%u, [%s, #%s%d]%s", CPnum, CRd, tbl_regs[get_nibble(inst, 4)], direction ? "" : "-", offset, writeback?"!":"");
416
    else
417
        dbg_printf("\t%u, cr%u, [%s], #%s%d", CPnum, CRd, tbl_regs[get_nibble(inst, 4)], direction ? "" : "-", offset);
418 419 420
    return 0;
}

421
static WORD thumb_disasm_hireg(WORD inst, ADDRESS64 *addr)
422 423 424 425 426 427 428 429 430 431
{
    short dst = inst & 0x07;
    short src = (inst >> 3) & 0x07;
    short h2  = (inst >> 6) & 0x01;
    short h1  = (inst >> 7) & 0x01;
    short op  = (inst >> 8) & 0x03;

    if (h1) dst += 8;
    if (h2) src += 8;

432 433 434 435 436 437
    if (op == 2 && dst == src) /* mov rx, rx */
    {
        dbg_printf("\n\tnop");
        return 0;
    }

438
    if (op == 3)
439
        dbg_printf("\n\tb%sx\t%s", h1?"l":"", tbl_regs[src]);
440
    else
441
        dbg_printf("\n\t%s\t%s, %s", tbl_hiops_t[op], tbl_regs[dst], tbl_regs[src]);
442 443 444 445

    return 0;
}

446 447 448 449 450 451 452 453 454 455 456
static WORD thumb_disasm_aluop(WORD inst, ADDRESS64 *addr)
{
    short dst = inst & 0x07;
    short src = (inst >> 3) & 0x07;
    short op  = (inst >> 6) & 0x0f;

    dbg_printf("\n\t%s\t%s, %s", tbl_aluops_t[op], tbl_regs[dst], tbl_regs[src]);

    return 0;
}

457
static WORD thumb_disasm_pushpop(WORD inst, ADDRESS64 *addr)
458 459 460 461 462 463 464 465 466 467 468 469 470 471 472
{
    short lrpc = (inst >> 8)  & 0x01;
    short load = (inst >> 11) & 0x01;
    short i;
    short last;

    for (i=7;i>=0;i--)
        if ((inst>>i) & 1) break;
    last = i;

    dbg_printf("\n\t%s\t{", load ? "pop" : "push");

    for (i=0;i<=7;i++)
        if ((inst>>i) & 1)
        {
473 474
            if (i == last) dbg_printf("%s", tbl_regs[i]);
            else dbg_printf("%s, ", tbl_regs[i]);
475 476
        }
    if (lrpc)
477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
        dbg_printf("%s%s", last ? ", " : "", load ? "pc" : "lr");

    dbg_printf("}");
    return 0;
}

static WORD thumb_disasm_blocktrans(WORD inst, ADDRESS64 *addr)
{
    short load = (inst >> 11) & 0x01;
    short i;
    short last;

    for (i=7;i>=0;i--)
        if ((inst>>i) & 1) break;
    last = i;

    dbg_printf("\n\t%s\t%s!, {", load ? "ldmia" : "stmia", tbl_regs[(inst >> 8) & 0x07]);

    for (i=0;i<=7;i++)
        if ((inst>>i) & 1)
        {
            if (i == last) dbg_printf("%s", tbl_regs[i]);
            else dbg_printf("%s, ", tbl_regs[i]);
        }
501 502 503 504 505

    dbg_printf("}");
    return 0;
}

506 507 508 509 510 511
static WORD thumb_disasm_swi(WORD inst, ADDRESS64 *addr)
{
    dbg_printf("\n\tswi\t#%d", inst & 0x00ff);
    return 0;
}

512 513 514
static WORD thumb_disasm_condbranch(WORD inst, ADDRESS64 *addr)
{
    WORD offset = inst & 0x00ff;
515 516
    dbg_printf("\n\tb%s\t", tbl_cond[(inst >> 8) & 0x0f]);
    db_printsym(addr->Offset + offset);
517 518 519
    return 0;
}

520 521 522 523 524 525 526 527 528 529 530 531
static WORD thumb_disasm_uncondbranch(WORD inst, ADDRESS64 *addr)
{
    short offset = (inst & 0x07ff) << 1;

    if (offset & 0x0800) offset |= 0xf000;
    offset += 4;

    dbg_printf("\n\tb\t");
    db_printsym(addr->Offset + offset);
    return 0;
}

532 533 534 535 536 537 538 539 540
static WORD thumb_disasm_loadadr(WORD inst, ADDRESS64 *addr)
{
    WORD src = (inst >> 11) & 0x01;
    WORD offset = (inst & 0xff) << 2;

    dbg_printf("\n\tadd\t%s, %s, #%d", tbl_regs[(inst >> 8) & 0x07], src ? "sp" : "pc", offset);
    return 0;
}

541
static WORD thumb_disasm_ldrpcrel(WORD inst, ADDRESS64 *addr)
542 543
{
    WORD offset = (inst & 0xff) << 2;
544
    dbg_printf("\n\tldr\t%s, [pc, #%u]", tbl_regs[(inst >> 8) & 0x07], offset);
545 546 547
    return 0;
}

548
static WORD thumb_disasm_ldrsprel(WORD inst, ADDRESS64 *addr)
549 550
{
    WORD offset = (inst & 0xff) << 2;
551
    dbg_printf("\n\t%s\t%s, [sp, #%u]", (inst & 0x0800)?"ldr":"str", tbl_regs[(inst >> 8) & 0x07], offset);
552 553 554
    return 0;
}

555 556 557 558 559 560 561 562 563 564
static WORD thumb_disasm_addsprel(WORD inst, ADDRESS64 *addr)
{
    WORD offset = (inst & 0x7f) << 2;
    if ((inst >> 7) & 0x01)
        dbg_printf("\n\tsub\tsp, sp, #%u", offset);
    else
        dbg_printf("\n\tadd\tsp, sp, #%u", offset);
    return 0;
}

565
static WORD thumb_disasm_ldrimm(WORD inst, ADDRESS64 *addr)
566 567
{
    WORD offset = (inst & 0x07c0) >> 6;
568 569
    dbg_printf("\n\t%s%s\t%s, [%s, #%u]", (inst & 0x0800)?"ldr":"str", (inst & 0x1000)?"b":"",
               tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst & 0x1000)?offset:(offset << 2));
570 571 572
    return 0;
}

573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594
static WORD thumb_disasm_ldrhimm(WORD inst, ADDRESS64 *addr)
{
    WORD offset = (inst & 0x07c0) >> 5;
    dbg_printf("\n\t%s\t%s, [%s, #%u]", (inst & 0x0800)?"ldrh":"strh",
               tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], offset);
    return 0;
}

static WORD thumb_disasm_ldrreg(WORD inst, ADDRESS64 *addr)
{
    dbg_printf("\n\t%s%s\t%s, [%s, %s]", (inst & 0x0800)?"ldr":"str", (inst & 0x0400)?"b":"",
               tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], tbl_regs[(inst >> 6) & 0x07]);
    return 0;
}

static WORD thumb_disasm_ldrsreg(WORD inst, ADDRESS64 *addr)
{
    dbg_printf("\n\t%s\t%s, [%s, %s]", tbl_sregops_t[(inst >> 10) & 0x03],
               tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], tbl_regs[(inst >> 6) & 0x07]);
    return 0;
}

595
static WORD thumb_disasm_immop(WORD inst, ADDRESS64 *addr)
596 597
{
    WORD op = (inst >> 11) & 0x03;
598
    dbg_printf("\n\t%s\t%s, #%u", tbl_immops_t[op], tbl_regs[(inst >> 8) & 0x07], inst & 0xff);
599 600 601
    return 0;
}

602 603 604 605 606 607
static WORD thumb_disasm_nop(WORD inst, ADDRESS64 *addr)
{
    dbg_printf("\n\tnop");
    return 0;
}

608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629
static WORD thumb_disasm_addsub(WORD inst, ADDRESS64 *addr)
{
    WORD op = (inst >> 9) & 0x01;
    WORD immediate = (inst >> 10) & 0x01;

    dbg_printf("\n\t%s\t%s, %s, ", op ? "sub" : "add",
               tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07]);
    if (immediate)
        dbg_printf("#%d", (inst >> 6) & 0x07);
    else
        dbg_printf("%s", tbl_regs[(inst >> 6) & 0x07]);
    return 0;
}

static WORD thumb_disasm_movshift(WORD inst, ADDRESS64 *addr)
{
    WORD op = (inst >> 11) & 0x03;
    dbg_printf("\n\t%s\t%s, %s, #%u", tbl_shifts[op],
               tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst >> 6) & 0x1f);
    return 0;
}

630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649
static UINT thumb2_disasm_srtrans(UINT inst, ADDRESS64 *addr)
{
    UINT fromsr = (inst >> 21) & 0x03;
    UINT sysreg = inst & 0xff;

    if (fromsr == 3 && get_nibble(inst,4) == 0x0f && sysreg <= 20)
    {
        dbg_printf("\n\tmrs\t%s, %s", tbl_regs[get_nibble(inst, 2)], tbl_special_regs_t2[sysreg]);
        return 0;
    }

    if (fromsr == 0 && sysreg <= 20)
    {
        dbg_printf("\n\tmsr\t%s, %s", tbl_special_regs_t2[sysreg], tbl_regs[get_nibble(inst, 4)]);
        return 0;
    }

    return inst;
}

650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671
static UINT thumb2_disasm_hint(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 8) & 0x07;
    WORD op2 = inst & 0xff;

    if (op1) return inst;

    if (op2 <= 4)
    {
        dbg_printf("\n\t%s", tbl_hints_t2[op2]);
        return 0;
    }

    if (op2 & 0xf0)
    {
        dbg_printf("\n\tdbg\t#%u", get_nibble(inst, 0));
        return 0;
    }

    return inst;
}

672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696
static UINT thumb2_disasm_miscctrl(UINT inst, ADDRESS64 *addr)
{
    WORD op = (inst >> 4) & 0x0f;

    switch (op)
    {
    case 2:
        dbg_printf("\n\tclrex");
        break;
    case 4:
        dbg_printf("\n\tdsb\t#%u", get_nibble(inst, 0));
        break;
    case 5:
        dbg_printf("\n\tdmb\t#%u", get_nibble(inst, 0));
        break;
    case 6:
        dbg_printf("\n\tisb\t#%u", get_nibble(inst, 0));
        break;
    default:
        return inst;
    }

    return 0;
}

697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721
static UINT thumb2_disasm_branch(UINT inst, ADDRESS64 *addr)
{
    UINT S  = (inst >> 26) & 0x01;
    UINT L  = (inst >> 14) & 0x01;
    UINT I1 = !(((inst >> 13) & 0x01) ^ S);
    UINT C  = !((inst >> 12) & 0x01);
    UINT I2 = !(((inst >> 11) & 0x01) ^ S);
    UINT offset = (inst & 0x000007ff) << 1;

    if (C)
    {
        offset |= I1 << 19 | I2 << 18 | (inst & 0x003f0000) >> 4;
        if (S) offset |= 0x0fff << 20;
    }
    else
    {
        offset |= I1 << 23 | I2 << 22 | (inst & 0x03ff0000) >> 4;
        if (S) offset |= 0xff << 24;
    }

    dbg_printf("\n\tb%s%s\t", L ? "l" : "", C ? tbl_cond[(inst >> 22) & 0x0f] : "");
    db_printsym(addr->Offset + offset + 4);
    return 0;
}

722 723 724 725 726 727 728 729 730 731
static UINT thumb2_disasm_misc(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 20) & 0x03;
    WORD op2 = (inst >> 4) & 0x03;

    if (get_nibble(inst, 4) != get_nibble(inst, 0))
        return inst;

    if (op1 == 3 && op2 == 0)
    {
732
        dbg_printf("\n\tclz\t%s, %s", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
733 734 735 736 737
        return 0;
    }

    if (op1 == 1)
    {
738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764
        dbg_printf("\n\t%s\t%s, %s", tbl_miscops_t2[op2], tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 0)]);
        return 0;
    }

    return inst;
}

static UINT thumb2_disasm_dataprocessingreg(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 20) & 0x07;
    WORD op2 = (inst >> 4) & 0x0f;

    if (!op2)
    {
        dbg_printf("\n\t%s%s\t%s, %s, %s", tbl_shifts[op1 >> 1], (op1 & 1)?"s":"",
                   tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 4)],
                   tbl_regs[get_nibble(inst, 0)]);
        return 0;
    }

    if ((op2 & 0x0C) == 0x08 && get_nibble(inst, 4) == 0x0f)
    {
        dbg_printf("\n\t%sxt%s\t%s, %s", (op1 & 1)?"u":"s", (op1 & 4)?"b":"h",
                   tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
        if (op2 & 0x03)
            dbg_printf(", ROR #%u", (op2 & 3) * 8);
765 766 767 768 769 770
        return 0;
    }

    return inst;
}

771 772 773 774 775 776 777 778 779 780
static UINT thumb2_disasm_mul(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 20) & 0x07;
    WORD op2 = (inst >> 4) & 0x03;

    if (op1)
        return inst;

    if (op2 == 0 && get_nibble(inst, 3) != 0xf)
    {
781
        dbg_printf("\n\tmla\t%s, %s, %s, %s", tbl_regs[get_nibble(inst, 2)],
782 783 784 785 786 787 788 789
                                                tbl_regs[get_nibble(inst, 4)],
                                                tbl_regs[get_nibble(inst, 0)],
                                                tbl_regs[get_nibble(inst, 3)]);
        return 0;
    }

    if (op2 == 0 && get_nibble(inst, 3) == 0xf)
    {
790
        dbg_printf("\n\tmul\t%s, %s, %s", tbl_regs[get_nibble(inst, 2)],
791 792 793 794 795 796 797
                                            tbl_regs[get_nibble(inst, 4)],
                                            tbl_regs[get_nibble(inst, 0)]);
        return 0;
    }

    if (op2 == 1)
    {
798
        dbg_printf("\n\tmls\t%s, %s, %s, %s", tbl_regs[get_nibble(inst, 2)],
799 800 801 802 803 804 805 806 807
                                                tbl_regs[get_nibble(inst, 4)],
                                                tbl_regs[get_nibble(inst, 0)],
                                                tbl_regs[get_nibble(inst, 3)]);
        return 0;
    }

    return inst;
}

808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831
static UINT thumb2_disasm_longmuldiv(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 20) & 0x07;
    WORD op2 = (inst >> 4) & 0x0f;

    if (op2 == 0)
    {
        switch (op1)
        {
        case 0:
            dbg_printf("\n\tsmull\t");
            break;
        case 2:
            dbg_printf("\n\tumull\t");
            break;
        case 4:
            dbg_printf("\n\tsmlal\t");
            break;
        case 6:
            dbg_printf("\n\tumlal\t");
            break;
        default:
            return inst;
        }
832
        dbg_printf("%s, %s, %s, %s", tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 2)],
833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849
                                       tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        return 0;
    }

    if (op2 == 0xffff)
    {
        switch (op1)
        {
        case 1:
            dbg_printf("\n\tsdiv\t");
            break;
        case 3:
            dbg_printf("\n\tudiv\t");
            break;
        default:
            return inst;
        }
850
        dbg_printf("%s, %s, %s", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 4)],
851 852 853 854 855 856 857
                                   tbl_regs[get_nibble(inst, 0)]);
        return 0;
    }

    return inst;
}

858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897
static UINT thumb2_disasm_str(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 21) & 0x07;
    WORD op2 = (inst >> 6) & 0x3f;

    if ((op1 & 0x03) == 3) return inst;

    if (!(op1 & 0x04) && inst & 0x0800)
    {
        int offset;
        dbg_printf("\n\tstr%s\t%s, [%s", tbl_width_t2[op1 & 0x03], tbl_regs[get_nibble(inst, 3)],
                   tbl_regs[get_nibble(inst, 4)]);

        offset = inst & 0xff;
        if (!(inst & 0x0200)) offset *= -1;

        if (!(inst & 0x0400) && (inst & 0x0100)) dbg_printf("], #%i", offset);
        else if (inst & 0x0400) dbg_printf(", #%i]%s", offset, (inst & 0x0100)?"!":"");
        else return inst;
        return 0;
    }

    if (!(op1 & 0x04) && !op2)
    {
        dbg_printf("\n\tstr%s\t%s, [%s, %s, LSL #%u]", tbl_width_t2[op1 & 0x03],
                   tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)],
                   tbl_regs[get_nibble(inst, 0)], (inst >> 4) & 0x3);
        return 0;
    }

    if (op1 & 0x04)
    {
        dbg_printf("\n\tstr%s\t%s, [%s, #%u]", tbl_width_t2[op1 & 0x03],
                   tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)], inst & 0x0fff);
        return 0;
    }

    return inst;
}

898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947
static UINT thumb2_disasm_ldrword(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 23) & 0x01;
    WORD op2 = (inst >> 6) & 0x3f;
    int offset;

    if (get_nibble(inst, 4) == 0x0f)
    {
        offset = inst & 0x0fff;

        if (!op1) offset *= -1;
        offset += 3;

        dbg_printf("\n\tldr\t%s, ", tbl_regs[get_nibble(inst, 3)]);
        db_printsym(addr->Offset + offset);
        return 0;
    }

    if (!op1 && !op2)
    {
        dbg_printf("\n\tldr\t%s, [%s, %s, LSL #%u]", tbl_regs[get_nibble(inst, 3)],
                   tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)], (inst >> 4) & 0x3);
        return 0;
    }

    if (!op1 && (op2 & 0x3c) == 0x38)
    {
        dbg_printf("\n\tldrt\t%s, [%s, #%u]", tbl_regs[get_nibble(inst, 3)],
                   tbl_regs[get_nibble(inst, 4)], inst & 0xff);
        return 0;
    }

    dbg_printf("\n\tldr\t%s, [%s", tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)]);

    if (op1)
    {
        dbg_printf(", #%u]", inst & 0x0fff);
        return 0;
    }

    offset = inst & 0xff;
    if (!(inst & 0x0200)) offset *= -1;

    if (!(inst & 0x0400) && (inst & 0x0100)) dbg_printf("], #%i", offset);
    else if (inst & 0x0400) dbg_printf(", #%i]%s", offset, (inst & 0x0100)?"!":"");
    else return inst;

    return 0;
}

948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980
static UINT thumb2_disasm_preload(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 23) & 0x03;

    if (!(op1 & 0x01) && !((inst >> 6) & 0x3f) && get_nibble(inst, 4) != 15)
    {
        WORD shift = (inst >> 4) & 0x03;
        dbg_printf("\n\t%s\t[%s, %s", op1?"pli":"pld", tbl_regs[get_nibble(inst, 4)],
                   tbl_regs[get_nibble(inst, 0)]);
        if (shift) dbg_printf(", lsl #%u]", shift);
        else dbg_printf("]");
        return 0;
    }

    if (get_nibble(inst, 4) != 15)
    {
        dbg_printf("\n\t%s\t[%s, #%d]", (op1 & 0x02)?"pli":"pld", tbl_regs[get_nibble(inst, 4)],
                   (op1 & 0x01)?(inst & 0x0fff):(-1 * (inst & 0xff)));
        return 0;
    }

    if (get_nibble(inst, 4) == 15)
    {
        int offset = inst & 0x0fff;
        if (!op1) offset *= -1;
        dbg_printf("\n\t%s\t", (op1 & 0x02)?"pli":"pld");
        db_printsym(addr->Offset + offset + 4);
        return 0;
    }

    return inst;
}

981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042
static UINT thumb2_disasm_ldrnonword(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 23) & 0x03;
    WORD hw  = (inst >> 21) & 0x01;

    if (!(op1 & 0x01) && !((inst >> 6) & 0x3f) && get_nibble(inst, 4) != 15)
    {
        WORD shift = (inst >> 4) & 0x03;
        dbg_printf("\n\t%s%s\t%s, [%s, %s", op1?"ldrs":"ldr", hw?"h":"b",
                   tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)],
                   tbl_regs[get_nibble(inst, 0)]);
        if (shift) dbg_printf(", lsl #%u]", shift);
        else dbg_printf("]");
        return 0;
    }

    if (!(op1 & 0x01) && ((inst >> 8) & 0x0f) == 14 && get_nibble(inst, 4) != 15)
    {
        WORD offset = inst & 0xff;
        dbg_printf("\n\t%s%s\t%s, [%s", op1?"ldrs":"ldr", hw?"ht":"bt",
                   tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)]);
        if (offset) dbg_printf(", #%u]", offset);
        else dbg_printf("]");
        return 0;
    }

    if (get_nibble(inst, 4) != 15)
    {
        int offset;

        dbg_printf("\n\t%s%s\t%s, [%s", (op1 & 0x02)?"ldrs":"ldr", hw?"h":"b",
                   tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)]);

        if (op1 & 0x01)
        {
            dbg_printf(", #%u]", inst & 0x0fff);
            return 0;
        }

        offset = inst & 0xff;
        if (!(inst & 0x0200)) offset *= -1;

        if (!(inst & 0x0400) && (inst & 0x0100)) dbg_printf("], #%i", offset);
        else if (inst & 0x0400) dbg_printf(", #%i]%s", offset, (inst & 0x0100)?"!":"");
        else return inst;

        return 0;
    }

    if (get_nibble(inst, 4) == 15)
    {
        int offset = inst & 0x0fff;
        if (!op1) offset *= -1;
        dbg_printf("\n\t%s%s\t%s, ", (op1 & 0x02)?"ldrs":"ldr", hw?"h":"b",
                   tbl_regs[get_nibble(inst, 3)]);
        db_printsym(addr->Offset + offset + 4);
        return 0;
    }

    return inst;
}

1043 1044 1045 1046 1047
static UINT thumb2_disasm_dataprocessing(UINT inst, ADDRESS64 *addr)
{
    WORD op = (inst >> 20) & 0x1f;
    WORD imm5 = ((inst >> 10) & 0x1c) + ((inst >> 6) & 0x03);

1048 1049 1050
    switch (op)
    {
    case 0:
1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062
    {
        WORD offset = ((inst >> 15) & 0x0800) + ((inst >> 4) & 0x0700) + (inst & 0xff);
        if (get_nibble(inst, 4) == 15)
        {
            dbg_printf("\n\tadr\t%s, ", tbl_regs[get_nibble(inst, 2)]);
            db_printsym(addr->Offset + offset + 4);
        }
        else
            dbg_printf("\n\taddw\t%s, %s, #%u", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    }
1063 1064
    case 4:
    case 12:
1065 1066 1067 1068 1069 1070 1071
    {
        WORD offset = ((inst >> 15) & 0x0800) + ((inst >> 4) & 0xf000) +
                      ((inst >>  4) & 0x0700) + (inst & 0xff);
        dbg_printf("\n\t%s\t%s, #%u", op == 12 ? "movt" : "movw", tbl_regs[get_nibble(inst, 2)],
                   offset);
        return 0;
    }
1072
    case 10:
1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085
    {
        int offset = ((inst >> 15) & 0x0800) + ((inst >> 4) & 0x0700) + (inst & 0xff);
        if (get_nibble(inst, 4) == 15)
        {
            offset *= -1;
            dbg_printf("\n\tadr\t%s, ", tbl_regs[get_nibble(inst, 2)]);
            db_printsym(addr->Offset + offset + 4);
        }
        else
            dbg_printf("\n\tsubw\t%s, %s, #%u", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    }
1086 1087 1088 1089
    case 16:
    case 18:
    case 24:
    case 26:
1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
    {
        BOOL sign = op < 24;
        WORD sh = (inst >> 21) & 0x01;
        WORD sat = (inst & 0x1f);
        if (sign) sat++;
        if (imm5)
            dbg_printf("\n\t%s\t%s, #%u, %s, %s #%u", sign ? "ssat" : "usat",
                       tbl_regs[get_nibble(inst, 2)], sat, tbl_regs[get_nibble(inst, 4)],
                       sh ? "asr" : "lsl", imm5);
        else
            dbg_printf("\n\t%s\t%s, #%u, %s", sign ? "ssat" : "usat", tbl_regs[get_nibble(inst, 2)],
                       sat, tbl_regs[get_nibble(inst, 4)]);
        return 0;
    }
1104 1105
    case 20:
    case 28:
1106 1107 1108 1109 1110 1111
    {
        WORD width = (inst & 0x1f) + 1;
        dbg_printf("\n\t%s\t%s, %s, #%u, #%u", op == 28 ? "ubfx" : "sbfx",
                   tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 4)], imm5, width);
        return 0;
    }
1112
    case 22:
1113 1114 1115 1116 1117 1118 1119 1120 1121
    {
        WORD msb = (inst & 0x1f) + 1 - imm5;
        if (get_nibble(inst, 4) == 15)
            dbg_printf("\n\tbfc\t%s, #%u, #%u", tbl_regs[get_nibble(inst, 2)], imm5, msb);
        else
            dbg_printf("\n\tbfi\t%s, %s, #%u, #%u", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], imm5, msb);
        return 0;
    }
1122 1123 1124
    default:
        return inst;
    }
1125 1126
}

1127 1128 1129 1130
static UINT thumb2_disasm_dataprocessingmod(UINT inst, ADDRESS64 *addr)
{
    WORD op = (inst >> 21) & 0x0f;
    WORD sf = (inst >> 20) & 0x01;
1131
    WORD offset = ((inst >> 15) & 0x0800) + ((inst >> 4) & 0x0700) + (inst & 0xff);
1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199

    /* FIXME: use ThumbExpandImm_C */

    switch (op)
    {
    case 0:
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\ttst\t%s, #%u", tbl_regs[get_nibble(inst, 4)], offset);
        else
            dbg_printf("\n\tand%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 1:
        dbg_printf("\n\tbic%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 2:
        if (get_nibble(inst, 4) == 15)
            dbg_printf("\n\tmov%s\t%s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)], offset);
        else
            dbg_printf("\n\torr%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 3:
        if (get_nibble(inst, 4) == 15)
            dbg_printf("\n\tmvn%s\t%s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)], offset);
        else
            dbg_printf("\n\torn%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 4:
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\tteq\t%s, #%u", tbl_regs[get_nibble(inst, 4)], offset);
        else
            dbg_printf("\n\teor%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 8:
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\tcmn\t%s, #%u", tbl_regs[get_nibble(inst, 4)], offset);
        else
            dbg_printf("\n\tadd%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 10:
        dbg_printf("\n\tadc%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 11:
        dbg_printf("\n\tsbc%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 13:
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\tcmp\t%s, #%u", tbl_regs[get_nibble(inst, 4)], offset);
        else
            dbg_printf("\n\tsub%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    case 14:
        dbg_printf("\n\trsb%s\t%s, %s, #%u", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    default:
        return inst;
    }
}

1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293
static UINT thumb2_disasm_dataprocessingshift(UINT inst, ADDRESS64 *addr)
{
    WORD op = (inst >> 21) & 0x0f;
    WORD sf = (inst >> 20) & 0x01;
    WORD imm5 = ((inst >> 10) & 0x1c) + ((inst >> 6) & 0x03);
    WORD type = (inst >> 4) & 0x03;

    if (!imm5 && (type == 1 || type == 2)) imm5 = 32;
    else if (!imm5 && type == 3) type = 4;

    switch (op)
    {
    case 0:
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\ttst\t%s, %s", tbl_regs[get_nibble(inst, 4)],
                       tbl_regs[get_nibble(inst, 0)]);
        else
            dbg_printf("\n\tand%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 1:
        dbg_printf("\n\tbic%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 2:
        if (get_nibble(inst, 4) == 15)
        {
            if (type == 4)
                dbg_printf("\n\trrx%s\t%s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
            else if (!type && !imm5)
                dbg_printf("\n\tmov%s\t%s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
            else
                dbg_printf("\n\t%s%s\t%s, %s, #%u", tbl_shifts[type], sf ? "s" : "", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)], imm5);
            return 0;
        }
        else
            dbg_printf("\n\torr%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 3:
        if (get_nibble(inst, 4) == 15)
            dbg_printf("\n\tmvn%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        else
            dbg_printf("\n\torn%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 4:
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\tteq\t%s, %s", tbl_regs[get_nibble(inst, 4)],
                       tbl_regs[get_nibble(inst, 0)]);
        else
            dbg_printf("\n\teor%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 8:
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\tcmn\t%s, %s", tbl_regs[get_nibble(inst, 4)],
                       tbl_regs[get_nibble(inst, 0)]);
        else
            dbg_printf("\n\tadd%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 10:
        dbg_printf("\n\tadc%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 11:
        dbg_printf("\n\tsbc%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 13:
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\tcmp\t%s, %s", tbl_regs[get_nibble(inst, 4)],
                       tbl_regs[get_nibble(inst, 0)]);
        else
            dbg_printf("\n\tsub%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    case 14:
        dbg_printf("\n\trsb%s\t%s, %s, %s", sf ? "s" : "", tbl_regs[get_nibble(inst, 2)],
                   tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
        break;
    default:
        return inst;
    }

    if (type == 4)
        dbg_printf(", rrx");
    else if (type || imm5)
        dbg_printf(", %s #%u", tbl_shifts[type], imm5);
    return 0;
}

1294 1295 1296 1297
static UINT thumb2_disasm_coprocdat(UINT inst, ADDRESS64 *addr)
{
    WORD opc2 = (inst >> 5) & 0x07;

1298 1299 1300
    dbg_printf("\n\tcdp%s\tp%u, #%u, cr%u, cr%u, cr%u", (inst & 0x10000000)?"2":"",
               get_nibble(inst, 2), get_nibble(inst, 5), get_nibble(inst, 3),
               get_nibble(inst, 4), get_nibble(inst, 0));
1301

1302
    if (opc2) dbg_printf(", #%u", opc2);
1303 1304 1305
    return 0;
}

1306 1307 1308 1309 1310
static UINT thumb2_disasm_coprocmov1(UINT inst, ADDRESS64 *addr)
{
    WORD opc1 = (inst >> 21) & 0x07;
    WORD opc2 = (inst >> 5) & 0x07;

1311 1312 1313
    dbg_printf("\n\t%s%s\tp%u, #%u, %s, cr%u, cr%u", (inst & 0x00100000)?"mrc":"mcr",
               (inst & 0x10000000)?"2":"", get_nibble(inst, 2), opc1,
               tbl_regs[get_nibble(inst, 3)], get_nibble(inst, 4), get_nibble(inst, 0));
1314

1315
    if (opc2) dbg_printf(", #%u", opc2);
1316 1317 1318
    return 0;
}

1319 1320 1321 1322 1323 1324 1325 1326 1327
static UINT thumb2_disasm_coprocmov2(UINT inst, ADDRESS64 *addr)
{
    dbg_printf("\n\t%s%s\tp%u, #%u, %s, %s, cr%u", (inst & 0x00100000)?"mrrc":"mcrr",
               (inst & 0x10000000)?"2":"", get_nibble(inst, 2), get_nibble(inst, 1),
               tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)], get_nibble(inst, 0));

    return 0;
}

1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359
static UINT thumb2_disasm_coprocdatatrans(UINT inst, ADDRESS64 *addr)
{
    WORD indexing  = (inst >> 24) & 0x01;
    WORD direction = (inst >> 23) & 0x01;
    WORD translen  = (inst >> 22) & 0x01;
    WORD writeback = (inst >> 21) & 0x01;
    WORD load      = (inst >> 20) & 0x01;
    short offset    = (inst & 0xff) << 2;

    if (!direction) offset *= -1;

    dbg_printf("\n\t%s%s%s", load ? "ldc" : "stc", (inst & 0x10000000)?"2":"", translen ? "l" : "");
    if (indexing)
    {
        if (load && get_nibble(inst, 4) == 15)
        {
            dbg_printf("\tp%u, cr%u, ", get_nibble(inst, 2), get_nibble(inst, 3));
            db_printsym(addr->Offset + offset + 4);
        }
        else
            dbg_printf("\tp%u, cr%u, [%s, #%d]%s", get_nibble(inst, 2), get_nibble(inst, 3), tbl_regs[get_nibble(inst, 4)], offset, writeback?"!":"");
    }
    else
    {
        if (writeback)
            dbg_printf("\tp%u, cr%u, [%s], #%d", get_nibble(inst, 2), get_nibble(inst, 3), tbl_regs[get_nibble(inst, 4)], offset);
        else
            dbg_printf("\tp%u, cr%u, [%s], {%u}", get_nibble(inst, 2), get_nibble(inst, 3), tbl_regs[get_nibble(inst, 4)], inst & 0xff);
    }
    return 0;
}

1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388
static UINT thumb2_disasm_ldrstrmul(UINT inst, ADDRESS64 *addr)
{
    short load      = (inst >> 20) & 0x01;
    short writeback = (inst >> 21) & 0x01;
    short decbefore = (inst >> 24) & 0x01;
    short i;
    short last=15;
    for (i=15;i>=0;i--)
        if ((inst>>i) & 1)
        {
            last = i;
            break;
        }

    if (writeback && get_nibble(inst, 4) == 13)
        dbg_printf("\n\t%s\t{", load ? "pop" : "push");
    else
        dbg_printf("\n\t%s%s\t%s%s, {", load ? "ldm" : "stm", decbefore ? "db" : "ia",
                   tbl_regs[get_nibble(inst, 4)], writeback ? "!" : "");
    for (i=0;i<=15;i++)
        if ((inst>>i) & 1)
        {
            if (i == last) dbg_printf("%s", tbl_regs[i]);
            else dbg_printf("%s, ", tbl_regs[i]);
        }
    dbg_printf("}");
    return 0;
}

1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455
static UINT thumb2_disasm_ldrstrextbr(UINT inst, ADDRESS64 *addr)
{
    WORD op1 = (inst >> 23) & 0x03;
    WORD op2 = (inst >> 20) & 0x03;
    WORD op3 = (inst >>  4) & 0x0f;
    WORD indexing  = (inst >> 24) & 0x01;
    WORD direction = (inst >> 23) & 0x01;
    WORD writeback = (inst >> 21) & 0x01;
    WORD load      = (inst >> 20) & 0x01;
    short offset   = (inst & 0xff) << 2;

    if (op1 == 1 && op2 == 1 && op3 < 2)
    {
        WORD halfword = (inst >> 4) & 0x01;
        if (halfword)
            dbg_printf("\n\ttbh\t [%s, %s, lsl #1]", tbl_regs[get_nibble(inst, 4)],
                       tbl_regs[get_nibble(inst, 0)]);
        else
            dbg_printf("\n\ttbb\t [%s, %s]", tbl_regs[get_nibble(inst, 4)],
                       tbl_regs[get_nibble(inst, 0)]);
        return 0;
    }

    if (op1 == 0 && op2 < 2)
    {
        if (get_nibble(inst, 2) == 15)
            dbg_printf("\n\tldrex\t %s, [%s, #%u]", tbl_regs[get_nibble(inst, 3)],
                       tbl_regs[get_nibble(inst, 4)], offset);
        else
            dbg_printf("\n\tstrex\t %s, %s, [%s, #%u]", tbl_regs[get_nibble(inst, 2)],
                       tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)], offset);
        return 0;
    }

    if (op1 == 1 && op2 < 2)
    {
        WORD halfword = (inst >> 4) & 0x01;
        if (get_nibble(inst, 0) == 15)
            dbg_printf("\n\tldrex%s\t %s, [%s]", halfword ? "h" : "b",
                       tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)]);
        else
            dbg_printf("\n\tstrex%s\t %s, %s, [%s]", halfword ? "h" : "b",
                       tbl_regs[get_nibble(inst, 0)], tbl_regs[get_nibble(inst, 3)],
                       tbl_regs[get_nibble(inst, 4)]);
        return 0;
    }

    if (!direction) offset *= -1;
    dbg_printf("\n\t%s\t", load ? "ldrd" : "strd");
    if (indexing)
    {
        if (load && get_nibble(inst, 4) == 15)
        {
            dbg_printf("%s, %s, ", tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 2)]);
            db_printsym(addr->Offset + offset + 4);
        }
        else
            dbg_printf("%s, %s, [%s, #%d]%s", tbl_regs[get_nibble(inst, 3)],
                       tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 4)], offset,
                       writeback?"!":"");
    }
    else
        dbg_printf("%s, %s, [%s], #%d", tbl_regs[get_nibble(inst, 3)],
                   tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 4)], offset);
    return 0;
}

1456 1457 1458 1459
struct inst_arm
{
        UINT mask;
        UINT pattern;
1460
        UINT (*func)(UINT, ADDRESS64*);
1461 1462 1463 1464
};

static const struct inst_arm tbl_arm[] = {
    { 0x0e000000, 0x0a000000, arm_disasm_branch },
1465 1466
    { 0x0fc000f0, 0x00000090, arm_disasm_mul },
    { 0x0f8000f0, 0x00800090, arm_disasm_longmul },
1467
    { 0x0fb00ff0, 0x01000090, arm_disasm_swp },
1468
    { 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
1469
    { 0x0ffffff0, 0x012fff10, arm_disasm_branchxchg },
1470 1471 1472 1473
    { 0x0fbf0fff, 0x010f0000, arm_disasm_mrstrans },
    { 0x0dbef000, 0x0128f000, arm_disasm_msrtrans },
    { 0x0fb00000, 0x03000000, arm_disasm_wordmov },
    { 0x0fffffff, 0x0320f000, arm_disasm_nop },
1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
    { 0x0c000000, 0x00000000, arm_disasm_dataprocessing },
    { 0x0c000000, 0x04000000, arm_disasm_singletrans },
    { 0x0e000000, 0x08000000, arm_disasm_blocktrans },
    { 0x0f000000, 0x0f000000, arm_disasm_swi },
    { 0x0f000010, 0x0e000010, arm_disasm_coproctrans },
    { 0x0f000010, 0x0e000000, arm_disasm_coprocdataop },
    { 0x0e000000, 0x0c000000, arm_disasm_coprocdatatrans },
    { 0x00000000, 0x00000000, NULL }
};

1484 1485 1486 1487
struct inst_thumb16
{
        WORD mask;
        WORD pattern;
1488
        WORD (*func)(WORD, ADDRESS64*);
1489 1490 1491 1492
};

static const struct inst_thumb16 tbl_thumb16[] = {
    { 0xfc00, 0x4400, thumb_disasm_hireg },
1493
    { 0xfc00, 0x4000, thumb_disasm_aluop },
1494 1495
    { 0xf600, 0xb400, thumb_disasm_pushpop },
    { 0xf000, 0xc000, thumb_disasm_blocktrans },
1496
    { 0xff00, 0xdf00, thumb_disasm_swi },
1497
    { 0xf000, 0xd000, thumb_disasm_condbranch },
1498
    { 0xf800, 0xe000, thumb_disasm_uncondbranch },
1499
    { 0xf000, 0xa000, thumb_disasm_loadadr },
1500 1501
    { 0xf800, 0x4800, thumb_disasm_ldrpcrel },
    { 0xf000, 0x9000, thumb_disasm_ldrsprel },
1502
    { 0xff00, 0xb000, thumb_disasm_addsprel },
1503
    { 0xe000, 0x6000, thumb_disasm_ldrimm },
1504 1505 1506
    { 0xf000, 0x8000, thumb_disasm_ldrhimm },
    { 0xf200, 0x5000, thumb_disasm_ldrreg },
    { 0xf200, 0x5200, thumb_disasm_ldrsreg },
1507 1508
    { 0xe000, 0x2000, thumb_disasm_immop },
    { 0xff00, 0xbf00, thumb_disasm_nop },
1509
    { 0xf800, 0x1800, thumb_disasm_addsub },
1510
    { 0xe000, 0x0000, thumb_disasm_movshift },
1511 1512 1513
    { 0x0000, 0x0000, NULL }
};

1514
static const struct inst_arm tbl_thumb32[] = {
1515 1516 1517
    { 0xfff0f000, 0xf3e08000, thumb2_disasm_srtrans },
    { 0xfff0f000, 0xf3808000, thumb2_disasm_srtrans },
    { 0xfff0d000, 0xf3a08000, thumb2_disasm_hint },
1518
    { 0xfff0d000, 0xf3b08000, thumb2_disasm_miscctrl },
1519
    { 0xf8008000, 0xf0008000, thumb2_disasm_branch },
1520
    { 0xffc0f0c0, 0xfa80f080, thumb2_disasm_misc },
1521
    { 0xff80f000, 0xfa00f000, thumb2_disasm_dataprocessingreg },
1522
    { 0xff8000c0, 0xfb000000, thumb2_disasm_mul },
1523 1524
    { 0xff8000f0, 0xfb800000, thumb2_disasm_longmuldiv },
    { 0xff8000f0, 0xfb8000f0, thumb2_disasm_longmuldiv },
1525
    { 0xff100000, 0xf8000000, thumb2_disasm_str },
1526
    { 0xff700000, 0xf8500000, thumb2_disasm_ldrword },
1527
    { 0xfe70f000, 0xf810f000, thumb2_disasm_preload },
1528
    { 0xfe500000, 0xf8100000, thumb2_disasm_ldrnonword },
1529
    { 0xfa008000, 0xf2000000, thumb2_disasm_dataprocessing },
1530
    { 0xfa008000, 0xf0000000, thumb2_disasm_dataprocessingmod },
1531
    { 0xfe008000, 0xea000000, thumb2_disasm_dataprocessingshift },
1532
    { 0xef000010, 0xee000000, thumb2_disasm_coprocdat },
1533
    { 0xef000010, 0xee000010, thumb2_disasm_coprocmov1 },
1534
    { 0xefe00000, 0xec400000, thumb2_disasm_coprocmov2 },
1535
    { 0xee000000, 0xec000000, thumb2_disasm_coprocdatatrans },
1536
    { 0xfe402000, 0xe8000000, thumb2_disasm_ldrstrmul },
1537
    { 0xfe400000, 0xe8400000, thumb2_disasm_ldrstrextbr },
1538 1539 1540
    { 0x00000000, 0x00000000, NULL }
};

1541 1542 1543 1544 1545 1546 1547 1548 1549
/***********************************************************************
 *              disasm_one_insn
 *
 * Disassemble instruction at 'addr'. addr is changed to point to the
 * start of the next instruction.
 */
void be_arm_disasm_one_insn(ADDRESS64 *addr, int display)
{
    struct inst_arm *a_ptr = (struct inst_arm *)&tbl_arm;
1550
    struct inst_thumb16 *t_ptr = (struct inst_thumb16 *)&tbl_thumb16;
1551
    struct inst_arm *t2_ptr = (struct inst_arm *)&tbl_thumb32;
1552
    UINT inst;
1553
    WORD tinst;
1554 1555 1556 1557 1558 1559 1560
    int size;
    int matched = 0;

    char tmp[64];
    DWORD_PTR* pval;

    if (!memory_get_register(CV_ARM_CPSR, &pval, tmp, sizeof(tmp)))
1561
        dbg_printf("\n\tmemory_get_register failed: %s", tmp);
1562
    else
1563
        db_disasm_thumb = (*pval & 0x20) != 0;
1564 1565 1566 1567 1568

    db_display = display;

    if (!db_disasm_thumb)
    {
1569 1570
        size = ARM_INSN_SIZE;
        inst = db_get_inst( memory_to_linear_addr(addr), size );
1571
        while (a_ptr->func) {
1572
            if ((inst & a_ptr->mask) == a_ptr->pattern) {
1573 1574 1575 1576
                    matched = 1;
                    break;
            }
            a_ptr++;
1577 1578 1579
        }

        if (!matched) {
1580 1581
            dbg_printf("\n\tUnknown ARM Instruction: %08x", inst);
            addr->Offset += size;
1582 1583 1584
        }
        else
        {
1585
            if (!a_ptr->func(inst, addr))
1586 1587
                addr->Offset += size;
        }
1588
        return;
1589 1590 1591
    }
    else
    {
1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604
        WORD *taddr = memory_to_linear_addr(addr);
        tinst = db_get_inst( taddr, THUMB_INSN_SIZE );
        switch (tinst & 0xf800)
        {
            case 0xe800:
            case 0xf000:
            case 0xf800:
                size = THUMB2_INSN_SIZE;
                taddr++;
                inst = db_get_inst( taddr, THUMB_INSN_SIZE );
                inst |= (tinst << 16);

                while (t2_ptr->func) {
1605
                    if ((inst & t2_ptr->mask) == t2_ptr->pattern) {
1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619
                            matched = 1;
                            break;
                    }
                    t2_ptr++;
                }

                if (!matched) {
                    dbg_printf("\n\tUnknown Thumb2 Instruction: %08x", inst);
                    addr->Offset += size;
                }
                else
                {
                    if (!t2_ptr->func(inst, addr))
                        addr->Offset += size;
1620
                }
1621 1622 1623 1624 1625 1626 1627
                return;
            default:
                break;
        }

        size = THUMB_INSN_SIZE;
        while (t_ptr->func) {
1628
            if ((tinst & t_ptr->mask) == t_ptr->pattern) {
1629 1630 1631 1632
                    matched = 1;
                    break;
            }
            t_ptr++;
1633 1634 1635
        }

        if (!matched) {
1636 1637
            dbg_printf("\n\tUnknown Thumb Instruction: %04x", tinst);
            addr->Offset += size;
1638 1639 1640
        }
        else
        {
1641
            if (!t_ptr->func(tinst, addr))
1642 1643 1644
                addr->Offset += size;
        }
        return;
1645 1646 1647
    }
}

1648
static BOOL be_arm_get_addr(HANDLE hThread, const dbg_ctx_t *ctx,
1649
                            enum be_cpu_addr bca, ADDRESS64* addr)
1650 1651 1652 1653
{
    switch (bca)
    {
    case be_cpu_addr_pc:
1654
        return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.Pc);
1655
    case be_cpu_addr_stack:
1656
        return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.Sp);
1657
    case be_cpu_addr_frame:
1658
        return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->ctx.R11);
1659 1660 1661 1662
    }
    return FALSE;
}

1663
static BOOL be_arm_get_register_info(int regno, enum be_cpu_addr* kind)
1664
{
1665 1666 1667 1668 1669 1670
    switch (regno)
    {
    case CV_ARM_PC:  *kind = be_cpu_addr_pc; return TRUE;
    case CV_ARM_R0 + 11: *kind = be_cpu_addr_frame; return TRUE;
    case CV_ARM_SP:  *kind = be_cpu_addr_stack; return TRUE;
    }
1671 1672 1673
    return FALSE;
}

1674
static void be_arm_single_step(dbg_ctx_t *ctx, BOOL enable)
1675 1676 1677
{
}

1678
static void be_arm_print_context(HANDLE hThread, const dbg_ctx_t *ctx, int all_regs)
1679
{
1680 1681 1682 1683
    static const char condflags[] = "NZCV";
    int i;
    char        buf[8];

1684
    switch (ctx->ctx.Cpsr & 0x1F)
1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698
    {
    case 0:  strcpy(buf, "User26"); break;
    case 1:  strcpy(buf, "FIQ26"); break;
    case 2:  strcpy(buf, "IRQ26"); break;
    case 3:  strcpy(buf, "SVC26"); break;
    case 16: strcpy(buf, "User"); break;
    case 17: strcpy(buf, "FIQ"); break;
    case 18: strcpy(buf, "IRQ"); break;
    case 19: strcpy(buf, "SVC"); break;
    case 23: strcpy(buf, "ABT"); break;
    case 27: strcpy(buf, "UND"); break;
    default: strcpy(buf, "UNKNWN"); break;
    }

1699
    dbg_printf("Register dump:\n");
1700
    dbg_printf("%s %s Mode\n", (ctx->ctx.Cpsr & 0x20) ? "Thumb" : "ARM", buf);
1701 1702 1703

    strcpy(buf, condflags);
    for (i = 0; buf[i]; i++)
1704
        if (!((ctx->ctx.Cpsr >> 26) & (1 << (sizeof(condflags) - i))))
1705 1706
            buf[i] = '-';

1707
    dbg_printf(" Pc:%08x Sp:%08x Lr:%08x Cpsr:%08x(%s)\n",
1708
               ctx->ctx.Pc, ctx->ctx.Sp, ctx->ctx.Lr, ctx->ctx.Cpsr, buf);
1709
    dbg_printf(" r0:%08x r1:%08x r2:%08x r3:%08x\n",
1710
               ctx->ctx.R0, ctx->ctx.R1, ctx->ctx.R2, ctx->ctx.R3);
1711
    dbg_printf(" r4:%08x r5:%08x r6:%08x r7:%08x\n",
1712
               ctx->ctx.R4, ctx->ctx.R5, ctx->ctx.R6, ctx->ctx.R7);
1713
    dbg_printf(" r8:%08x r9:%08x r10:%08x r11:%08x r12:%08x\n",
1714
               ctx->ctx.R8, ctx->ctx.R9, ctx->ctx.R10, ctx->ctx.R11, ctx->ctx.R12);
1715 1716

    if (all_regs) dbg_printf( "Floating point ARM dump not implemented\n" );
1717 1718
}

1719
static void be_arm_print_segment_info(HANDLE hThread, const dbg_ctx_t *ctx)
1720 1721 1722 1723 1724
{
}

static struct dbg_internal_var be_arm_ctx[] =
{
1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741
    {CV_ARM_R0 +  0,    "r0",           (void*)FIELD_OFFSET(CONTEXT, R0),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  1,    "r1",           (void*)FIELD_OFFSET(CONTEXT, R1),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  2,    "r2",           (void*)FIELD_OFFSET(CONTEXT, R2),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  3,    "r3",           (void*)FIELD_OFFSET(CONTEXT, R3),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  4,    "r4",           (void*)FIELD_OFFSET(CONTEXT, R4),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  5,    "r5",           (void*)FIELD_OFFSET(CONTEXT, R5),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  6,    "r6",           (void*)FIELD_OFFSET(CONTEXT, R6),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  7,    "r7",           (void*)FIELD_OFFSET(CONTEXT, R7),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  8,    "r8",           (void*)FIELD_OFFSET(CONTEXT, R8),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  9,    "r9",           (void*)FIELD_OFFSET(CONTEXT, R9),     dbg_itype_unsigned_int},
    {CV_ARM_R0 +  10,   "r10",          (void*)FIELD_OFFSET(CONTEXT, R10),    dbg_itype_unsigned_int},
    {CV_ARM_R0 +  11,   "r11",          (void*)FIELD_OFFSET(CONTEXT, R11),    dbg_itype_unsigned_int},
    {CV_ARM_R0 +  12,   "r12",          (void*)FIELD_OFFSET(CONTEXT, R12),    dbg_itype_unsigned_int},
    {CV_ARM_SP,         "sp",           (void*)FIELD_OFFSET(CONTEXT, Sp),     dbg_itype_unsigned_int},
    {CV_ARM_LR,         "lr",           (void*)FIELD_OFFSET(CONTEXT, Lr),     dbg_itype_unsigned_int},
    {CV_ARM_PC,         "pc",           (void*)FIELD_OFFSET(CONTEXT, Pc),     dbg_itype_unsigned_int},
    {CV_ARM_CPSR,       "cpsr",         (void*)FIELD_OFFSET(CONTEXT, Cpsr),   dbg_itype_unsigned_int},
1742
    {0,                 NULL,           0,                                         dbg_itype_none}
1743 1744
};

1745
static BOOL be_arm_is_step_over_insn(const void* insn)
1746
{
1747
    dbg_printf("be_arm_is_step_over_insn: not done\n");
1748 1749 1750
    return FALSE;
}

1751
static BOOL be_arm_is_function_return(const void* insn)
1752
{
1753
    dbg_printf("be_arm_is_function_return: not done\n");
1754 1755 1756
    return FALSE;
}

1757
static BOOL be_arm_is_break_insn(const void* insn)
1758
{
1759
    dbg_printf("be_arm_is_break_insn: not done\n");
1760 1761 1762
    return FALSE;
}

1763
static BOOL be_arm_is_func_call(const void* insn, ADDRESS64* callee)
1764 1765 1766 1767
{
    return FALSE;
}

1768
static BOOL be_arm_is_jump(const void* insn, ADDRESS64* jumpee)
1769 1770 1771 1772
{
    return FALSE;
}

1773
static BOOL be_arm_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
1774
                                 dbg_ctx_t *ctx, enum be_xpoint_type type,
1775
                                 void* addr, unsigned *val, unsigned size)
1776 1777 1778 1779 1780 1781
{
    SIZE_T              sz;

    switch (type)
    {
    case be_xpoint_break:
1782 1783
        if (!size) return FALSE;
        if (!pio->read(hProcess, addr, val, 4, &sz) || sz != 4) return FALSE;
1784 1785
    default:
        dbg_printf("Unknown/unsupported bp type %c\n", type);
1786
        return FALSE;
1787
    }
1788
    return TRUE;
1789 1790
}

1791
static BOOL be_arm_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
1792
                                 dbg_ctx_t *ctx, enum be_xpoint_type type,
1793
                                 void* addr, unsigned val, unsigned size)
1794 1795 1796 1797 1798 1799
{
    SIZE_T              sz;

    switch (type)
    {
    case be_xpoint_break:
1800 1801
        if (!size) return FALSE;
        if (!pio->write(hProcess, addr, &val, 4, &sz) || sz == 4) return FALSE;
1802 1803 1804
        break;
    default:
        dbg_printf("Unknown/unsupported bp type %c\n", type);
1805
        return FALSE;
1806
    }
1807
    return TRUE;
1808 1809
}

1810
static BOOL be_arm_is_watchpoint_set(const dbg_ctx_t *ctx, unsigned idx)
1811
{
1812
    dbg_printf("be_arm_is_watchpoint_set: not done\n");
1813 1814 1815
    return FALSE;
}

1816
static void be_arm_clear_watchpoint(dbg_ctx_t *ctx, unsigned idx)
1817
{
1818
    dbg_printf("be_arm_clear_watchpoint: not done\n");
1819 1820
}

1821
static int be_arm_adjust_pc_for_break(dbg_ctx_t *ctx, BOOL way)
1822
{
1823
    INT step = (ctx->ctx.Cpsr & 0x20) ? 2 : 4;
1824

1825 1826
    if (way)
    {
1827
        ctx->ctx.Pc -= step;
1828
        return -step;
1829
    }
1830
    ctx->ctx.Pc += step;
1831
    return step;
1832 1833
}

1834 1835 1836 1837 1838 1839
static BOOL be_arm_get_context(HANDLE thread, dbg_ctx_t *ctx)
{
    ctx->ctx.ContextFlags = CONTEXT_ALL;
    return GetThreadContext(thread, &ctx->ctx);
}

1840 1841 1842 1843 1844
static BOOL be_arm_set_context(HANDLE thread, const dbg_ctx_t *ctx)
{
    return SetThreadContext(thread, &ctx->ctx);
}

1845
#define REG(f,n,t,r)  {f, n, t, FIELD_OFFSET(CONTEXT, r), sizeof(((CONTEXT*)NULL)->r)}
1846 1847

static struct gdb_register be_arm_gdb_register_map[] = {
1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864
    REG("core", "r0",   NULL,       R0),
    REG(NULL,   "r1",   NULL,       R1),
    REG(NULL,   "r2",   NULL,       R2),
    REG(NULL,   "r3",   NULL,       R3),
    REG(NULL,   "r4",   NULL,       R4),
    REG(NULL,   "r5",   NULL,       R5),
    REG(NULL,   "r6",   NULL,       R6),
    REG(NULL,   "r7",   NULL,       R7),
    REG(NULL,   "r8",   NULL,       R8),
    REG(NULL,   "r9",   NULL,       R9),
    REG(NULL,   "r10",  NULL,       R10),
    REG(NULL,   "r11",  NULL,       R11),
    REG(NULL,   "r12",  NULL,       R12),
    REG(NULL,   "sp",   "data_ptr", Sp),
    REG(NULL,   "lr",   "code_ptr", Lr),
    REG(NULL,   "pc",   "code_ptr", Pc),
    REG(NULL,   "cpsr", NULL,       Cpsr),
1865 1866
};

1867 1868
struct backend_cpu be_arm =
{
1869
    IMAGE_FILE_MACHINE_ARMNT,
1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882
    4,
    be_cpu_linearize,
    be_cpu_build_addr,
    be_arm_get_addr,
    be_arm_get_register_info,
    be_arm_single_step,
    be_arm_print_context,
    be_arm_print_segment_info,
    be_arm_ctx,
    be_arm_is_step_over_insn,
    be_arm_is_function_return,
    be_arm_is_break_insn,
    be_arm_is_func_call,
1883
    be_arm_is_jump,
1884 1885 1886 1887 1888 1889
    be_arm_disasm_one_insn,
    be_arm_insert_Xpoint,
    be_arm_remove_Xpoint,
    be_arm_is_watchpoint_set,
    be_arm_clear_watchpoint,
    be_arm_adjust_pc_for_break,
1890
    be_arm_get_context,
1891
    be_arm_set_context,
1892 1893
    be_arm_gdb_register_map,
    ARRAY_SIZE(be_arm_gdb_register_map),
1894 1895
};
#endif