asmshader.y 74.2 KB
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 /*
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 * Direct3D shader assembler
 *
 * Copyright 2008 Stefan Dösinger
 * Copyright 2009 Matteo Bruni
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
 */

%{
#include "config.h"
#include "wine/port.h"
#include "wine/debug.h"

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#include "d3dcompiler_private.h"
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WINE_DEFAULT_DEBUG_CHANNEL(asmshader);

struct asm_parser asm_ctx;

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void asmparser_message(struct asm_parser *ctx, const char *fmt, ...)
{
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    va_list args;

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    va_start(args, fmt);
    compilation_message(&ctx->messages, fmt, args);
    va_end(args);
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}

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static void asmshader_error(char const *s) {
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    asmparser_message(&asm_ctx, "Line %u: Error \"%s\" from bison\n", asm_ctx.line_no, s);
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    set_parse_status(&asm_ctx.status, PARSE_ERR);
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}
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static void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
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    /* We can have an additional offset without true relative addressing
     * ex. c2[ 4 ] */
    reg->regnum += rel->additional_offset;
    if(!rel->has_rel_reg) {
        reg->rel_reg = NULL;
    } else {
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        reg->rel_reg = d3dcompiler_alloc(sizeof(*reg->rel_reg));
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        if(!reg->rel_reg) {
            return;
        }
        reg->rel_reg->type = rel->type;
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        reg->rel_reg->u.swizzle = rel->swizzle;
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        reg->rel_reg->regnum = rel->rel_regnum;
    }
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}

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/* Needed lexer functions declarations */
int asmshader_lex(void);


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%}

%union {
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    struct {
        float           val;
        BOOL            integer;
    } immval;
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    BOOL                immbool;
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    unsigned int        regnum;
    struct shader_reg   reg;
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    DWORD               srcmod;
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    DWORD               writemask;
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    struct {
        DWORD           writemask;
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        DWORD           idx;
        DWORD           last;
    } wm_components;
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    DWORD               swizzle;
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    struct {
        DWORD           swizzle;
        DWORD           idx;
    } sw_components;
    DWORD               component;
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    struct {
        DWORD           mod;
        DWORD           shift;
    } modshift;
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    BWRITER_COMPARISON_TYPE comptype;
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    struct {
        DWORD           dclusage;
        unsigned int    regnum;
    } declaration;
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    BWRITERSAMPLER_TEXTURE_TYPE samplertype;
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    struct rel_reg      rel_reg;
    struct src_regs     sregs;
}

/* Common instructions between vertex and pixel shaders */
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%token INSTR_ADD
%token INSTR_NOP
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%token INSTR_MOV
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%token INSTR_SUB
%token INSTR_MAD
%token INSTR_MUL
%token INSTR_RCP
%token INSTR_RSQ
%token INSTR_DP3
%token INSTR_DP4
%token INSTR_MIN
%token INSTR_MAX
%token INSTR_SLT
%token INSTR_SGE
%token INSTR_ABS
%token INSTR_EXP
%token INSTR_LOG
%token INSTR_EXPP
%token INSTR_LOGP
%token INSTR_DST
%token INSTR_LRP
%token INSTR_FRC
%token INSTR_POW
%token INSTR_CRS
%token INSTR_SGN
%token INSTR_NRM
%token INSTR_SINCOS
%token INSTR_M4x4
%token INSTR_M4x3
%token INSTR_M3x4
%token INSTR_M3x3
%token INSTR_M3x2
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%token INSTR_DCL
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%token INSTR_DEF
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%token INSTR_DEFB
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%token INSTR_DEFI
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%token INSTR_REP
%token INSTR_ENDREP
%token INSTR_IF
%token INSTR_ELSE
%token INSTR_ENDIF
%token INSTR_BREAK
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%token INSTR_BREAKP
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%token INSTR_CALL
%token INSTR_CALLNZ
%token INSTR_LOOP
%token INSTR_RET
%token INSTR_ENDLOOP
%token INSTR_LABEL
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%token INSTR_SETP
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%token INSTR_TEXLDL

/* Vertex shader only instructions  */
%token INSTR_LIT
%token INSTR_MOVA
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/* Pixel shader only instructions   */
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%token INSTR_CND
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%token INSTR_CMP
%token INSTR_DP2ADD
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%token INSTR_TEXCOORD
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%token INSTR_TEXCRD
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%token INSTR_TEXKILL
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%token INSTR_TEX
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%token INSTR_TEXLD
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%token INSTR_TEXBEM
%token INSTR_TEXBEML
%token INSTR_TEXREG2AR
%token INSTR_TEXREG2GB
%token INSTR_TEXREG2RGB
%token INSTR_TEXM3x2PAD
%token INSTR_TEXM3x2TEX
%token INSTR_TEXM3x3PAD
%token INSTR_TEXM3x3SPEC
%token INSTR_TEXM3x3VSPEC
%token INSTR_TEXM3x3TEX
%token INSTR_TEXDP3TEX
%token INSTR_TEXM3x2DEPTH
%token INSTR_TEXDP3
%token INSTR_TEXM3x3
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%token INSTR_TEXDEPTH
%token INSTR_BEM
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%token INSTR_DSX
%token INSTR_DSY
%token INSTR_TEXLDP
%token INSTR_TEXLDB
%token INSTR_TEXLDD
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%token INSTR_PHASE
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/* Registers */
%token <regnum> REG_TEMP
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%token <regnum> REG_OUTPUT
%token <regnum> REG_INPUT
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%token <regnum> REG_CONSTFLOAT
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%token <regnum> REG_CONSTINT
%token <regnum> REG_CONSTBOOL
%token <regnum> REG_TEXTURE
%token <regnum> REG_SAMPLER
%token <regnum> REG_TEXCRDOUT
%token REG_OPOS
%token REG_OFOG
%token REG_OPTS
%token <regnum> REG_VERTEXCOLOR
%token <regnum> REG_FRAGCOLOR
%token REG_FRAGDEPTH
%token REG_VPOS
%token REG_VFACE
%token REG_ADDRESS
%token REG_LOOP
%token REG_PREDICATE
%token <regnum> REG_LABEL
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/* Version tokens */
%token VER_VS10
%token VER_VS11
%token VER_VS20
%token VER_VS2X
%token VER_VS30

%token VER_PS10
%token VER_PS11
%token VER_PS12
%token VER_PS13
%token VER_PS14
%token VER_PS20
%token VER_PS2X
%token VER_PS30

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/* Output modifiers */
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%token SHIFT_X2
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%token SHIFT_X4
%token SHIFT_X8
%token SHIFT_D2
%token SHIFT_D4
%token SHIFT_D8
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%token MOD_SAT
%token MOD_PP
%token MOD_CENTROID

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/* Compare tokens */
%token COMP_GT
%token COMP_LT
%token COMP_GE
%token COMP_LE
%token COMP_EQ
%token COMP_NE

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/* Source register modifiers */
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%token SMOD_BIAS
%token SMOD_SCALEBIAS
%token SMOD_DZ
%token SMOD_DW
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%token SMOD_ABS
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%token SMOD_NOT
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/* Sampler types */
%token SAMPTYPE_1D
%token SAMPTYPE_2D
%token SAMPTYPE_CUBE
%token SAMPTYPE_VOLUME

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/* Usage declaration tokens */
%token <regnum> USAGE_POSITION
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%token <regnum> USAGE_BLENDWEIGHT
%token <regnum> USAGE_BLENDINDICES
%token <regnum> USAGE_NORMAL
%token <regnum> USAGE_PSIZE
%token <regnum> USAGE_TEXCOORD
%token <regnum> USAGE_TANGENT
%token <regnum> USAGE_BINORMAL
%token <regnum> USAGE_TESSFACTOR
%token <regnum> USAGE_POSITIONT
%token <regnum> USAGE_COLOR
%token <regnum> USAGE_FOG
%token <regnum> USAGE_DEPTH
%token <regnum> USAGE_SAMPLE
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/* Misc stuff */
%token <component> COMPONENT
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%token <immval> IMMVAL
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%token <immbool> IMMBOOL
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%type <reg> dreg_name
%type <reg> dreg
%type <reg> sreg_name
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%type <reg> relreg_name
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%type <reg> sreg
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%type <srcmod> smod
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%type <writemask> writemask
%type <wm_components> wm_components
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%type <swizzle> swizzle
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%type <sw_components> sw_components
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%type <modshift> omods
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%type <modshift> omodifier
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%type <comptype> comp
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%type <declaration> dclusage
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%type <reg> dcl_inputreg
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%type <samplertype> sampdcl
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%type <rel_reg> rel_reg
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%type <reg> predicate
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%type <immval> immsum
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%type <sregs> sregs

%%

shader:               version_marker instructions
                        {
                            asm_ctx.funcs->end(&asm_ctx);
                        }

version_marker:       VER_VS10
                        {
                            TRACE("Vertex shader 1.0\n");
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                            create_vs10_parser(&asm_ctx);
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                        }
                    | VER_VS11
                        {
                            TRACE("Vertex shader 1.1\n");
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                            create_vs11_parser(&asm_ctx);
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                        }
                    | VER_VS20
                        {
                            TRACE("Vertex shader 2.0\n");
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                            create_vs20_parser(&asm_ctx);
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                        }
                    | VER_VS2X
                        {
                            TRACE("Vertex shader 2.x\n");
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                            create_vs2x_parser(&asm_ctx);
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                        }
                    | VER_VS30
                        {
                            TRACE("Vertex shader 3.0\n");
                            create_vs30_parser(&asm_ctx);
                        }
                    | VER_PS10
                        {
                            TRACE("Pixel  shader 1.0\n");
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                            create_ps10_parser(&asm_ctx);
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                        }
                    | VER_PS11
                        {
                            TRACE("Pixel  shader 1.1\n");
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                            create_ps11_parser(&asm_ctx);
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                        }
                    | VER_PS12
                        {
                            TRACE("Pixel  shader 1.2\n");
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                            create_ps12_parser(&asm_ctx);
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                        }
                    | VER_PS13
                        {
                            TRACE("Pixel  shader 1.3\n");
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                            create_ps13_parser(&asm_ctx);
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                        }
                    | VER_PS14
                        {
                            TRACE("Pixel  shader 1.4\n");
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                            create_ps14_parser(&asm_ctx);
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                        }
                    | VER_PS20
                        {
                            TRACE("Pixel  shader 2.0\n");
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                            create_ps20_parser(&asm_ctx);
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                        }
                    | VER_PS2X
                        {
                            TRACE("Pixel  shader 2.x\n");
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                            create_ps2x_parser(&asm_ctx);
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                        }
                    | VER_PS30
                        {
                            TRACE("Pixel  shader 3.0\n");
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                            create_ps30_parser(&asm_ctx);
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                        }

instructions:         /* empty */
                    | instructions complexinstr
                            {
                                /* Nothing to do */
                            }

complexinstr:         instruction
                            {

                            }
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                    | predicate instruction
                            {
                                TRACE("predicate\n");
                                asm_ctx.funcs->predicate(&asm_ctx, &$1);
                            }
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                    | '+' instruction
                            {
                                TRACE("coissue\n");
                                asm_ctx.funcs->coissue(&asm_ctx);
                            }
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instruction:          INSTR_ADD omods dreg ',' sregs
                            {
                                TRACE("ADD\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ADD, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_NOP
                            {
                                TRACE("NOP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NOP, 0, 0, 0, 0, 0, 0);
                            }
                    | INSTR_MOV omods dreg ',' sregs
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                            {
                                TRACE("MOV\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOV, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
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                    | INSTR_SUB omods dreg ',' sregs
                            {
                                TRACE("SUB\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SUB, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_MAD omods dreg ',' sregs
                            {
                                TRACE("MAD\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAD, $2.mod, $2.shift, 0, &$3, &$5, 3);
                            }
                    | INSTR_MUL omods dreg ',' sregs
                            {
                                TRACE("MUL\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MUL, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_RCP omods dreg ',' sregs
                            {
                                TRACE("RCP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RCP, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_RSQ omods dreg ',' sregs
                            {
                                TRACE("RSQ\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RSQ, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_DP3 omods dreg ',' sregs
                            {
                                TRACE("DP3\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP3, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_DP4 omods dreg ',' sregs
                            {
                                TRACE("DP4\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP4, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_MIN omods dreg ',' sregs
                            {
                                TRACE("MIN\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MIN, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_MAX omods dreg ',' sregs
                            {
                                TRACE("MAX\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAX, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_SLT omods dreg ',' sregs
                            {
                                TRACE("SLT\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SLT, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_SGE omods dreg ',' sregs
                            {
                                TRACE("SGE\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGE, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_ABS omods dreg ',' sregs
                            {
                                TRACE("ABS\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ABS, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_EXP omods dreg ',' sregs
                            {
                                TRACE("EXP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXP, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_LOG omods dreg ',' sregs
                            {
                                TRACE("LOG\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOG, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_LOGP omods dreg ',' sregs
                            {
                                TRACE("LOGP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOGP, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_EXPP omods dreg ',' sregs
                            {
                                TRACE("EXPP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXPP, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_DST omods dreg ',' sregs
                            {
                                TRACE("DST\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DST, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_LRP omods dreg ',' sregs
                            {
                                TRACE("LRP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LRP, $2.mod, $2.shift, 0, &$3, &$5, 3);
                            }
                    | INSTR_FRC omods dreg ',' sregs
                            {
                                TRACE("FRC\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_FRC, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_POW omods dreg ',' sregs
                            {
                                TRACE("POW\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_POW, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_CRS omods dreg ',' sregs
                            {
                                TRACE("CRS\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CRS, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_SGN omods dreg ',' sregs
                            {
                                TRACE("SGN\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGN, $2.mod, $2.shift, 0, &$3, &$5, 3);
                            }
                    | INSTR_NRM omods dreg ',' sregs
                            {
                                TRACE("NRM\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NRM, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_SINCOS omods dreg ',' sregs
                            {
                                TRACE("SINCOS\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SINCOS, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_M4x4 omods dreg ',' sregs
                            {
                                TRACE("M4x4\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_M4x3 omods dreg ',' sregs
                            {
                                TRACE("M4x3\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_M3x4 omods dreg ',' sregs
                            {
                                TRACE("M3x4\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_M3x3 omods dreg ',' sregs
                            {
                                TRACE("M3x3\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_M3x2 omods dreg ',' sregs
                            {
                                TRACE("M3x2\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x2, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
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                    | INSTR_DCL dclusage REG_OUTPUT
                            {
                                struct shader_reg reg;
                                TRACE("Output reg declaration\n");
                                ZeroMemory(&reg, sizeof(reg));
                                reg.type = BWRITERSPR_OUTPUT;
                                reg.regnum = $3;
                                reg.rel_reg = NULL;
                                reg.srcmod = 0;
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                                reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
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                                asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, &reg);
                            }
                    | INSTR_DCL dclusage REG_OUTPUT writemask
                            {
                                struct shader_reg reg;
                                TRACE("Output reg declaration\n");
                                ZeroMemory(&reg, sizeof(reg));
                                reg.type = BWRITERSPR_OUTPUT;
                                reg.regnum = $3;
                                reg.rel_reg = NULL;
                                reg.srcmod = 0;
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                                reg.u.writemask = $4;
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                                asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, &reg);
                            }
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                    | INSTR_DCL dclusage omods dcl_inputreg
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                            {
                                struct shader_reg reg;
                                TRACE("Input reg declaration\n");
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                                if($3.shift != 0) {
                                    asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
                                                      asm_ctx.line_no);
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                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
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                                }
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                                if(asm_ctx.shader->version == BWRITERPS_VERSION(2, 0) ||
                                    asm_ctx.shader->version == BWRITERPS_VERSION(2, 1)) {
                                    asmparser_message(&asm_ctx, "Line %u: Declaration not supported in PS 2\n",
                                                      asm_ctx.line_no);
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                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
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                                }
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                                ZeroMemory(&reg, sizeof(reg));
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                                reg.type = $4.type;
                                reg.regnum = $4.regnum;
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                                reg.rel_reg = NULL;
                                reg.srcmod = 0;
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                                reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
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                                asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, &reg);
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                            }
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                    | INSTR_DCL dclusage omods dcl_inputreg writemask
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                            {
                                struct shader_reg reg;
                                TRACE("Input reg declaration\n");
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                                if($3.shift != 0) {
                                    asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
                                                      asm_ctx.line_no);
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                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
618
                                }
619 620 621 622
                                if(asm_ctx.shader->version == BWRITERPS_VERSION(2, 0) ||
                                    asm_ctx.shader->version == BWRITERPS_VERSION(2, 1)) {
                                    asmparser_message(&asm_ctx, "Line %u: Declaration not supported in PS 2\n",
                                                      asm_ctx.line_no);
623
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
624
                                }
625
                                ZeroMemory(&reg, sizeof(reg));
626 627
                                reg.type = $4.type;
                                reg.regnum = $4.regnum;
628 629
                                reg.rel_reg = NULL;
                                reg.srcmod = 0;
630
                                reg.u.writemask = $5;
631
                                asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, &reg);
632
                            }
633
                    | INSTR_DCL omods dcl_inputreg
634 635 636 637 638 639
                            {
                                struct shader_reg reg;
                                TRACE("Input reg declaration\n");
                                if($2.shift != 0) {
                                    asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
                                                      asm_ctx.line_no);
640
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
641
                                }
642 643 644
                                if(asm_ctx.shader->type != ST_PIXEL) {
                                    asmparser_message(&asm_ctx, "Line %u: Declaration needs a semantic\n",
                                                      asm_ctx.line_no);
645
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
646
                                }
647
                                ZeroMemory(&reg, sizeof(reg));
648 649
                                reg.type = $3.type;
                                reg.regnum = $3.regnum;
650 651
                                reg.rel_reg = NULL;
                                reg.srcmod = 0;
652
                                reg.u.writemask = BWRITERSP_WRITEMASK_ALL;
653 654
                                asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, &reg);
                            }
655
                    | INSTR_DCL omods dcl_inputreg writemask
656 657 658 659 660 661
                            {
                                struct shader_reg reg;
                                TRACE("Input reg declaration\n");
                                if($2.shift != 0) {
                                    asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
                                                      asm_ctx.line_no);
662
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
663
                                }
664 665 666
                                if(asm_ctx.shader->type != ST_PIXEL) {
                                    asmparser_message(&asm_ctx, "Line %u: Declaration needs a semantic\n",
                                                      asm_ctx.line_no);
667
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
668
                                }
669
                                ZeroMemory(&reg, sizeof(reg));
670 671
                                reg.type = $3.type;
                                reg.regnum = $3.regnum;
672 673
                                reg.rel_reg = NULL;
                                reg.srcmod = 0;
674
                                reg.u.writemask = $4;
675 676
                                asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, &reg);
                            }
677
                    | INSTR_DCL sampdcl omods REG_SAMPLER
678 679
                            {
                                TRACE("Sampler declared\n");
680 681 682
                                if($3.shift != 0) {
                                    asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
                                                      asm_ctx.line_no);
683
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
684 685
                                }
                                asm_ctx.funcs->dcl_sampler(&asm_ctx, $2, $3.mod, $4, asm_ctx.line_no);
686
                            }
687 688 689 690 691 692
                    | INSTR_DCL omods REG_SAMPLER
                            {
                                TRACE("Sampler declared\n");
                                if($2.shift != 0) {
                                    asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
                                                      asm_ctx.line_no);
693
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
694 695 696 697
                                }
                                if(asm_ctx.shader->type != ST_PIXEL) {
                                    asmparser_message(&asm_ctx, "Line %u: Declaration needs a sampler type\n",
                                                      asm_ctx.line_no);
698
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
699 700 701
                                }
                                asm_ctx.funcs->dcl_sampler(&asm_ctx, BWRITERSTT_UNKNOWN, $2.mod, $3, asm_ctx.line_no);
                            }
702
                    | INSTR_DCL sampdcl omods dcl_inputreg
703 704 705 706
                            {
                                TRACE("Error rule: sampler decl of input reg\n");
                                asmparser_message(&asm_ctx, "Line %u: Sampler declarations of input regs is not valid\n",
                                                  asm_ctx.line_no);
707
                                set_parse_status(&asm_ctx.status,  PARSE_WARN);
708
                            }
709
                    | INSTR_DCL sampdcl omods REG_OUTPUT
710 711 712 713
                            {
                                TRACE("Error rule: sampler decl of output reg\n");
                                asmparser_message(&asm_ctx, "Line %u: Sampler declarations of output regs is not valid\n",
                                                  asm_ctx.line_no);
714
                                set_parse_status(&asm_ctx.status,  PARSE_WARN);
715
                            }
716 717 718
                    | INSTR_DEF REG_CONSTFLOAT ',' IMMVAL ',' IMMVAL ',' IMMVAL ',' IMMVAL
                            {
                                asm_ctx.funcs->constF(&asm_ctx, $2, $4.val, $6.val, $8.val, $10.val);
719 720 721 722
                            }
                    | INSTR_DEFI REG_CONSTINT ',' IMMVAL ',' IMMVAL ',' IMMVAL ',' IMMVAL
                            {
                                asm_ctx.funcs->constI(&asm_ctx, $2, $4.val, $6.val, $8.val, $10.val);
723
                            }
724 725 726 727
                    | INSTR_DEFB REG_CONSTBOOL ',' IMMBOOL
                            {
                                asm_ctx.funcs->constB(&asm_ctx, $2, $4);
                            }
728 729 730 731 732 733 734 735 736 737 738 739 740 741 742
                    | INSTR_REP sregs
                            {
                                TRACE("REP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_REP, 0, 0, 0, 0, &$2, 1);
                            }
                    | INSTR_ENDREP
                            {
                                TRACE("ENDREP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDREP, 0, 0, 0, 0, 0, 0);
                            }
                    | INSTR_IF sregs
                            {
                                TRACE("IF\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IF, 0, 0, 0, 0, &$2, 1);
                            }
743 744 745 746 747
                    | INSTR_IF comp sregs
                            {
                                TRACE("IFC\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IFC, 0, 0, $2, 0, &$3, 2);
                            }
748 749 750 751 752 753 754 755 756 757 758 759 760 761 762
                    | INSTR_ELSE
                            {
                                TRACE("ELSE\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ELSE, 0, 0, 0, 0, 0, 0);
                            }
                    | INSTR_ENDIF
                            {
                                TRACE("ENDIF\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDIF, 0, 0, 0, 0, 0, 0);
                            }
                    | INSTR_BREAK
                            {
                                TRACE("BREAK\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAK, 0, 0, 0, 0, 0, 0);
                            }
763 764 765 766 767
                    | INSTR_BREAK comp sregs
                            {
                                TRACE("BREAKC\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKC, 0, 0, $2, 0, &$3, 2);
                            }
768 769 770 771 772
                    | INSTR_BREAKP sregs
                            {
                                TRACE("BREAKP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKP, 0, 0, 0, 0, &$2, 1);
                            }
773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802
                    | INSTR_CALL sregs
                            {
                                TRACE("CALL\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CALL, 0, 0, 0, 0, &$2, 1);
                            }
                    | INSTR_CALLNZ sregs
                            {
                                TRACE("CALLNZ\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CALLNZ, 0, 0, 0, 0, &$2, 2);
                            }
                    | INSTR_LOOP sregs
                            {
                                TRACE("LOOP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOOP, 0, 0, 0, 0, &$2, 2);
                            }
                    | INSTR_RET
                            {
                                TRACE("RET\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RET, 0, 0, 0, 0, 0, 0);
                            }
                    | INSTR_ENDLOOP
                            {
                                TRACE("ENDLOOP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDLOOP, 0, 0, 0, 0, 0, 0);
                            }
                    | INSTR_LABEL sregs
                            {
                                TRACE("LABEL\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LABEL, 0, 0, 0, 0, &$2, 1);
                            }
803 804 805 806 807
                    | INSTR_SETP comp dreg ',' sregs
                            {
                                TRACE("SETP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SETP, 0, 0, $2, &$3, &$5, 2);
                            }
808 809 810 811 812 813 814 815 816 817 818 819 820 821 822
                    | INSTR_TEXLDL omods dreg ',' sregs
                            {
                                TRACE("TEXLDL\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDL, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_LIT omods dreg ',' sregs
                            {
                                TRACE("LIT\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LIT, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_MOVA omods dreg ',' sregs
                            {
                                TRACE("MOVA\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOVA, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
823 824 825 826 827
                    | INSTR_CND omods dreg ',' sregs
                            {
                                TRACE("CND\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CND, $2.mod, $2.shift, 0, &$3, &$5, 3);
                            }
828 829 830 831 832 833 834 835 836 837
                    | INSTR_CMP omods dreg ',' sregs
                            {
                                TRACE("CMP\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CMP, $2.mod, $2.shift, 0, &$3, &$5, 3);
                            }
                    | INSTR_DP2ADD omods dreg ',' sregs
                            {
                                TRACE("DP2ADD\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP2ADD, $2.mod, $2.shift, 0, &$3, &$5, 3);
                            }
838 839 840 841 842
                    | INSTR_TEXCOORD omods dreg
                            {
                                TRACE("TEXCOORD\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, 0, 0);
                            }
843 844 845 846 847 848
                    | INSTR_TEXCRD omods dreg ',' sregs
                            {
                                TRACE("TEXCRD\n");
                                /* texcoord and texcrd share the same opcode */
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
849 850 851 852 853
                    | INSTR_TEXKILL dreg
                            {
                                TRACE("TEXKILL\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXKILL, 0, 0, 0, &$2, 0, 0);
                            }
854 855 856 857 858
                    | INSTR_TEX omods dreg
                            {
                                TRACE("TEX\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, 0, 0);
                            }
859 860 861 862 863
                    | INSTR_TEXDEPTH omods dreg
                            {
                                TRACE("TEXDEPTH\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDEPTH, $2.mod, $2.shift, 0, &$3, 0, 0);
                            }
864 865 866 867 868 869 870 871 872 873 874 875 876 877
                    | INSTR_TEXLD omods dreg ',' sregs
                            {
                                TRACE("TEXLD\n");
                                /* There is more than one acceptable syntax for texld:
                                   with 1 sreg (PS 1.4) or
                                   with 2 sregs (PS 2.0+)
                                   Moreover, texld shares the same opcode as the tex instruction,
                                   so there are a total of 3 valid syntaxes
                                   These variations are handled in asmparser.c */
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_TEXLDP omods dreg ',' sregs
                            {
                                TRACE("TEXLDP\n");
878
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDP, $2.mod, $2.shift, 0, &$3, &$5, 2);
879 880 881 882
                            }
                    | INSTR_TEXLDB omods dreg ',' sregs
                            {
                                TRACE("TEXLDB\n");
883
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDB, $2.mod, $2.shift, 0, &$3, &$5, 2);
884
                            }
885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959
                    | INSTR_TEXBEM omods dreg ',' sregs
                            {
                                TRACE("TEXBEM\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEM, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXBEML omods dreg ',' sregs
                            {
                                TRACE("TEXBEML\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEML, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXREG2AR omods dreg ',' sregs
                            {
                                TRACE("TEXREG2AR\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2AR, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXREG2GB omods dreg ',' sregs
                            {
                                TRACE("TEXREG2GB\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2GB, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXREG2RGB omods dreg ',' sregs
                            {
                                TRACE("TEXREG2RGB\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2RGB, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXM3x2PAD omods dreg ',' sregs
                            {
                                TRACE("TEXM3x2PAD\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXM3x3PAD omods dreg ',' sregs
                            {
                                TRACE("INSTR_TEXM3x3PAD\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXM3x3SPEC omods dreg ',' sregs
                            {
                                TRACE("TEXM3x3SPEC\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3SPEC, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
                    | INSTR_TEXM3x3VSPEC omods dreg ',' sregs
                            {
                                TRACE("TEXM3x3VSPEC\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3VSPEC, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXM3x3TEX omods dreg ',' sregs
                            {
                                TRACE("TEXM3x3TEX\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXDP3TEX omods dreg ',' sregs
                            {
                                TRACE("TEXDP3TEX\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXM3x2DEPTH omods dreg ',' sregs
                            {
                                TRACE("TEXM3x2DEPTH\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2DEPTH, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXM3x2TEX omods dreg ',' sregs
                            {
                                TRACE("TEXM3x2TEX\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXDP3 omods dreg ',' sregs
                            {
                                TRACE("TEXDP3\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXM3x3 omods dreg ',' sregs
                            {
                                TRACE("TEXM3x3\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
960 961 962 963 964
                    | INSTR_BEM omods dreg ',' sregs
                            {
                                TRACE("BEM\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BEM, $2.mod, $2.shift, 0, &$3, &$5, 2);
                            }
965 966 967 968 969 970 971 972 973 974 975 976 977 978 979
                    | INSTR_DSX omods dreg ',' sregs
                            {
                                TRACE("DSX\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DSX, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_DSY omods dreg ',' sregs
                            {
                                TRACE("DSY\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DSY, $2.mod, $2.shift, 0, &$3, &$5, 1);
                            }
                    | INSTR_TEXLDD omods dreg ',' sregs
                            {
                                TRACE("TEXLDD\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDD, $2.mod, $2.shift, 0, &$3, &$5, 4);
                            }
980 981 982 983 984 985
                    | INSTR_PHASE
                            {
                                TRACE("PHASE\n");
                                asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_PHASE, 0, 0, 0, 0, 0, 0);
                            }

986 987 988 989 990

dreg:                 dreg_name rel_reg
                            {
                                $$.regnum = $1.regnum;
                                $$.type = $1.type;
991
                                $$.u.writemask = BWRITERSP_WRITEMASK_ALL;
992 993 994
                                $$.srcmod = BWRITERSPSM_NONE;
                                set_rel_reg(&$$, &$2);
                            }
995 996 997 998
                    | dreg_name writemask
                            {
                                $$.regnum = $1.regnum;
                                $$.type = $1.type;
999
                                $$.u.writemask = $2;
1000 1001 1002
                                $$.srcmod = BWRITERSPSM_NONE;
                                $$.rel_reg = NULL;
                            }
1003 1004 1005 1006 1007

dreg_name:            REG_TEMP
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_TEMP;
                        }
1008 1009 1010 1011 1012 1013
                    | REG_OUTPUT
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_OUTPUT;
                        }
                    | REG_INPUT
                        {
1014
                            $$.regnum = $1; $$.type = BWRITERSPR_INPUT;
1015 1016 1017 1018 1019
                        }
                    | REG_CONSTFLOAT
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register c%u is not a valid destination register\n",
                                              asm_ctx.line_no, $1);
1020
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1021 1022 1023
                        }
                    | REG_CONSTINT
                        {
1024
                            asmparser_message(&asm_ctx, "Line %u: Register i%u is not a valid destination register\n",
1025
                                              asm_ctx.line_no, $1);
1026
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1027 1028 1029 1030 1031
                        }
                    | REG_CONSTBOOL
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register b%u is not a valid destination register\n",
                                              asm_ctx.line_no, $1);
1032
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045
                        }
                    | REG_TEXTURE
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
                        }
                    | REG_TEXCRDOUT
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_TEXCRDOUT;
                        }
                    | REG_SAMPLER
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register s%u is not a valid destination register\n",
                                              asm_ctx.line_no, $1);
1046
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079
                        }
                    | REG_OPOS
                        {
                            $$.regnum = BWRITERSRO_POSITION; $$.type = BWRITERSPR_RASTOUT;
                        }
                    | REG_OPTS
                        {
                            $$.regnum = BWRITERSRO_POINT_SIZE; $$.type = BWRITERSPR_RASTOUT;
                        }
                    | REG_OFOG
                        {
                            $$.regnum = BWRITERSRO_FOG; $$.type = BWRITERSPR_RASTOUT;
                        }
                    | REG_VERTEXCOLOR
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_ATTROUT;
                        }
                    | REG_FRAGCOLOR
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_COLOROUT;
                        }
                    | REG_FRAGDEPTH
                        {
                            $$.regnum = 0; $$.type = BWRITERSPR_DEPTHOUT;
                        }
                    | REG_PREDICATE
                        {
                            $$.regnum = 0; $$.type = BWRITERSPR_PREDICATE;
                        }
                    | REG_VPOS
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register vPos is not a valid destination register\n",
                                              asm_ctx.line_no);
1080
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1081 1082 1083 1084 1085
                        }
                    | REG_VFACE
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register vFace is not a valid destination register\n",
                                              asm_ctx.line_no);
1086
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1087 1088 1089 1090 1091 1092 1093 1094 1095 1096
                        }
                    | REG_ADDRESS
                        {
                            /* index 0 is hardcoded for the addr register */
                            $$.regnum = 0; $$.type = BWRITERSPR_ADDR;
                        }
                    | REG_LOOP
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register aL is not a valid destination register\n",
                                              asm_ctx.line_no);
1097
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1098
                        }
1099

1100 1101 1102 1103 1104
writemask:            '.' wm_components
                        {
                            if($2.writemask == SWIZZLE_ERR) {
                                asmparser_message(&asm_ctx, "Line %u: Invalid writemask specified\n",
                                                  asm_ctx.line_no);
1105
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135
                                /* Provide a correct writemask to prevent following complaints */
                                $$ = BWRITERSP_WRITEMASK_ALL;
                            }
                            else {
                                $$ = $2.writemask;
                                TRACE("Writemask: %x\n", $$);
                            }
                        }

wm_components:        COMPONENT
                        {
                            $$.writemask = 1 << $1;
                            $$.last = $1;
                            $$.idx = 1;
                        }
                    | wm_components COMPONENT
                        {
                            if($1.writemask == SWIZZLE_ERR || $1.idx == 4)
                                /* Wrong writemask */
                                $$.writemask = SWIZZLE_ERR;
                            else {
                                if($2 <= $1.last)
                                    $$.writemask = SWIZZLE_ERR;
                                else {
                                    $$.writemask = $1.writemask | (1 << $2);
                                    $$.idx = $1.idx + 1;
                                }
                            }
                        }

1136 1137 1138 1139 1140
swizzle:              /* empty */
                        {
                            $$ = BWRITERVS_NOSWIZZLE;
                            TRACE("Default swizzle: %08x\n", $$);
                        }
1141 1142 1143 1144 1145
                    | '.' sw_components
                        {
                            if($2.swizzle == SWIZZLE_ERR) {
                                asmparser_message(&asm_ctx, "Line %u: Invalid swizzle\n",
                                                  asm_ctx.line_no);
1146
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179
                                /* Provide a correct swizzle to prevent following complaints */
                                $$ = BWRITERVS_NOSWIZZLE;
                            }
                            else {
                                DWORD last, i;

                                $$ = $2.swizzle << BWRITERVS_SWIZZLE_SHIFT;
                                /* Fill the swizzle by extending the last component */
                                last = ($2.swizzle >> 2 * ($2.idx - 1)) & 0x03;
                                for(i = $2.idx; i < 4; i++){
                                    $$ |= last << (BWRITERVS_SWIZZLE_SHIFT + 2 * i);
                                }
                                TRACE("Got a swizzle: %08x\n", $$);
                            }
                        }

sw_components:        COMPONENT
                        {
                            $$.swizzle = $1;
                            $$.idx = 1;
                        }
                    | sw_components COMPONENT
                        {
                            if($1.idx == 4) {
                                /* Too many sw_components */
                                $$.swizzle = SWIZZLE_ERR;
                                $$.idx = 4;
                            }
                            else {
                                $$.swizzle = $1.swizzle | ($2 << 2 * $1.idx);
                                $$.idx = $1.idx + 1;
                            }
                        }
1180 1181 1182 1183 1184 1185

omods:                 /* Empty */
                        {
                            $$.mod = 0;
                            $$.shift = 0;
                        }
1186 1187 1188 1189 1190 1191
                    | omods omodifier
                        {
                            $$.mod = $1.mod | $2.mod;
                            if($1.shift && $2.shift) {
                                asmparser_message(&asm_ctx, "Line %u: More than one shift flag\n",
                                                  asm_ctx.line_no);
1192
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1193 1194 1195 1196 1197 1198
                                $$.shift = $1.shift;
                            } else {
                                $$.shift = $1.shift | $2.shift;
                            }
                        }

1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229
omodifier:            SHIFT_X2
                        {
                            $$.mod = 0;
                            $$.shift = 1;
                        }
                    | SHIFT_X4
                        {
                            $$.mod = 0;
                            $$.shift = 2;
                        }
                    | SHIFT_X8
                        {
                            $$.mod = 0;
                            $$.shift = 3;
                        }
                    | SHIFT_D2
                        {
                            $$.mod = 0;
                            $$.shift = 15;
                        }
                    | SHIFT_D4
                        {
                            $$.mod = 0;
                            $$.shift = 14;
                        }
                    | SHIFT_D8
                        {
                            $$.mod = 0;
                            $$.shift = 13;
                        }
                    | MOD_SAT
1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
                        {
                            $$.mod = BWRITERSPDM_SATURATE;
                            $$.shift = 0;
                        }
                    | MOD_PP
                        {
                            $$.mod = BWRITERSPDM_PARTIALPRECISION;
                            $$.shift = 0;
                        }
                    | MOD_CENTROID
                        {
                            $$.mod = BWRITERSPDM_MSAMPCENTROID;
                            $$.shift = 0;
                        }
1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254

sregs:                sreg
                        {
                            $$.reg[0] = $1;
                            $$.count = 1;
                        }
                    | sregs ',' sreg
                        {
                            if($$.count == MAX_SRC_REGS){
                                asmparser_message(&asm_ctx, "Line %u: Too many source registers in this instruction\n",
                                                  asm_ctx.line_no);
1255
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1256 1257 1258 1259 1260 1261 1262 1263 1264
                            }
                            else
                                $$.reg[$$.count++] = $3;
                        }

sreg:                   sreg_name rel_reg swizzle
                        {
                            $$.type = $1.type;
                            $$.regnum = $1.regnum;
1265
                            $$.u.swizzle = $3;
1266 1267 1268
                            $$.srcmod = BWRITERSPSM_NONE;
                            set_rel_reg(&$$, &$2);
                        }
1269 1270 1271 1272 1273 1274
                    | sreg_name rel_reg smod swizzle
                        {
                            $$.type = $1.type;
                            $$.regnum = $1.regnum;
                            set_rel_reg(&$$, &$2);
                            $$.srcmod = $3;
1275
                            $$.u.swizzle = $4;
1276 1277 1278 1279 1280 1281 1282
                        }
                    | '-' sreg_name rel_reg swizzle
                        {
                            $$.type = $2.type;
                            $$.regnum = $2.regnum;
                            $$.srcmod = BWRITERSPSM_NEG;
                            set_rel_reg(&$$, &$3);
1283
                            $$.u.swizzle = $4;
1284 1285 1286 1287 1288 1289 1290
                        }
                    | '-' sreg_name rel_reg smod swizzle
                        {
                            $$.type = $2.type;
                            $$.regnum = $2.regnum;
                            set_rel_reg(&$$, &$3);
                            switch($4) {
1291 1292 1293
                                case BWRITERSPSM_BIAS: $$.srcmod = BWRITERSPSM_BIASNEG; break;
                                case BWRITERSPSM_X2:   $$.srcmod = BWRITERSPSM_X2NEG;   break;
                                case BWRITERSPSM_SIGN: $$.srcmod = BWRITERSPSM_SIGNNEG; break;
1294
                                case BWRITERSPSM_ABS:  $$.srcmod = BWRITERSPSM_ABSNEG;  break;
1295 1296 1297
                                case BWRITERSPSM_DZ:
                                    asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: NEG and DZ\n",
                                                      asm_ctx.line_no);
1298
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
1299 1300 1301 1302
                                    break;
                                case BWRITERSPSM_DW:
                                    asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: NEG and DW\n",
                                                      asm_ctx.line_no);
1303
                                    set_parse_status(&asm_ctx.status,  PARSE_ERR);
1304
                                    break;
1305 1306 1307
                                default:
                                    FIXME("Unhandled combination of NEGATE and %u\n", $4);
                            }
1308
                            $$.u.swizzle = $5;
1309
                        }
1310 1311 1312 1313 1314
                    | IMMVAL '-' sreg_name rel_reg swizzle
                        {
                            if($1.val != 1.0 || (!$1.integer)) {
                                asmparser_message(&asm_ctx, "Line %u: Only \"1 - reg\" is valid for D3DSPSM_COMP, "
                                                  "%g - reg found\n", asm_ctx.line_no, $1.val);
1315
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1316 1317 1318 1319 1320 1321
                            }
                            /* Complement - not compatible with other source modifiers */
                            $$.type = $3.type;
                            $$.regnum = $3.regnum;
                            $$.srcmod = BWRITERSPSM_COMP;
                            set_rel_reg(&$$, &$4);
1322
                            $$.u.swizzle = $5;
1323 1324 1325 1326 1327 1328 1329
                        }
                    | IMMVAL '-' sreg_name rel_reg smod swizzle
                        {
                            /* For nicer error reporting */
                            if($1.val != 1.0 || (!$1.integer)) {
                                asmparser_message(&asm_ctx, "Line %u: Only \"1 - reg\" is valid for D3DSPSM_COMP\n",
                                                  asm_ctx.line_no);
1330
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1331 1332 1333 1334
                            } else {
                                asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: D3DSPSM_COMP and %s\n",
                                                  asm_ctx.line_no,
                                                  debug_print_srcmod($5));
1335
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1336 1337
                            }
                        }
1338 1339 1340 1341 1342 1343
                    | SMOD_NOT sreg_name swizzle
                        {
                            $$.type = $2.type;
                            $$.regnum = $2.regnum;
                            $$.rel_reg = NULL;
                            $$.srcmod = BWRITERSPSM_NOT;
1344
                            $$.u.swizzle = $3;
1345
                        }
1346 1347 1348 1349 1350 1351

rel_reg:               /* empty */
                        {
                            $$.has_rel_reg = FALSE;
                            $$.additional_offset = 0;
                        }
1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394
                    | '[' immsum ']'
                        {
                            $$.has_rel_reg = FALSE;
                            $$.additional_offset = $2.val;
                        }
                    | '[' relreg_name swizzle ']'
                        {
                            $$.has_rel_reg = TRUE;
                            $$.type = $2.type;
                            $$.additional_offset = 0;
                            $$.rel_regnum = $2.regnum;
                            $$.swizzle = $3;
                        }
                    | '[' immsum '+' relreg_name swizzle ']'
                        {
                            $$.has_rel_reg = TRUE;
                            $$.type = $4.type;
                            $$.additional_offset = $2.val;
                            $$.rel_regnum = $4.regnum;
                            $$.swizzle = $5;
                        }
                    | '[' relreg_name swizzle '+' immsum ']'
                        {
                            $$.has_rel_reg = TRUE;
                            $$.type = $2.type;
                            $$.additional_offset = $5.val;
                            $$.rel_regnum = $2.regnum;
                            $$.swizzle = $3;
                        }
                    | '[' immsum '+' relreg_name swizzle '+' immsum ']'
                        {
                            $$.has_rel_reg = TRUE;
                            $$.type = $4.type;
                            $$.additional_offset = $2.val + $7.val;
                            $$.rel_regnum = $4.regnum;
                            $$.swizzle = $5;
                        }

immsum:               IMMVAL
                        {
                            if(!$1.integer) {
                                asmparser_message(&asm_ctx, "Line %u: Unexpected float %f\n",
                                                  asm_ctx.line_no, $1.val);
1395
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1396 1397 1398 1399 1400 1401 1402 1403
                            }
                            $$.val = $1.val;
                        }
                    | immsum '+' IMMVAL
                        {
                            if(!$3.integer) {
                                asmparser_message(&asm_ctx, "Line %u: Unexpected float %f\n",
                                                  asm_ctx.line_no, $3.val);
1404
                                set_parse_status(&asm_ctx.status,  PARSE_ERR);
1405 1406 1407
                            }
                            $$.val = $1.val + $3.val;
                        }
1408

1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429
smod:                 SMOD_BIAS
                        {
                            $$ = BWRITERSPSM_BIAS;
                        }
                    | SHIFT_X2
                        {
                            $$ = BWRITERSPSM_X2;
                        }
                    | SMOD_SCALEBIAS
                        {
                            $$ = BWRITERSPSM_SIGN;
                        }
                    | SMOD_DZ
                        {
                            $$ = BWRITERSPSM_DZ;
                        }
                    | SMOD_DW
                        {
                            $$ = BWRITERSPSM_DW;
                        }
                    | SMOD_ABS
1430 1431 1432 1433
                        {
                            $$ = BWRITERSPSM_ABS;
                        }

1434 1435 1436 1437 1438 1439 1440 1441 1442
relreg_name:          REG_ADDRESS
                        {
                            $$.regnum = 0; $$.type = BWRITERSPR_ADDR;
                        }
                    | REG_LOOP
                        {
                            $$.regnum = 0; $$.type = BWRITERSPR_LOOP;
                        }

1443 1444 1445 1446
sreg_name:            REG_TEMP
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_TEMP;
                        }
1447 1448 1449 1450
                    | REG_OUTPUT
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register o%u is not a valid source register\n",
                                              asm_ctx.line_no, $1);
1451
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1452 1453 1454 1455 1456
                        }
                    | REG_INPUT
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_INPUT;
                        }
1457 1458 1459 1460
                    | REG_CONSTFLOAT
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_CONST;
                        }
1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
                    | REG_CONSTINT
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_CONSTINT;
                        }
                    | REG_CONSTBOOL
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_CONSTBOOL;
                        }
                    | REG_TEXTURE
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
                        }
                    | REG_TEXCRDOUT
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register oT%u is not a valid source register\n",
                                              asm_ctx.line_no, $1);
1477
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1478 1479 1480 1481 1482 1483 1484 1485 1486
                        }
                    | REG_SAMPLER
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_SAMPLER;
                        }
                    | REG_OPOS
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register oPos is not a valid source register\n",
                                              asm_ctx.line_no);
1487
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1488 1489 1490 1491 1492
                        }
                    | REG_OFOG
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register oFog is not a valid source register\n",
                                              asm_ctx.line_no);
1493
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1494 1495 1496 1497 1498
                        }
                    | REG_VERTEXCOLOR
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register oD%u is not a valid source register\n",
                                              asm_ctx.line_no, $1);
1499
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1500 1501 1502 1503 1504
                        }
                    | REG_FRAGCOLOR
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register oC%u is not a valid source register\n",
                                              asm_ctx.line_no, $1);
1505
                            set_parse_status(&asm_ctx.status,  PARSE_WARN);
1506 1507 1508 1509 1510
                        }
                    | REG_FRAGDEPTH
                        {
                            asmparser_message(&asm_ctx, "Line %u: Register oDepth is not a valid source register\n",
                                              asm_ctx.line_no);
1511
                            set_parse_status(&asm_ctx.status, PARSE_WARN);
1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536
                        }
                    | REG_PREDICATE
                        {
                            $$.regnum = 0; $$.type = BWRITERSPR_PREDICATE;
                        }
                    | REG_VPOS
                        {
                            $$.regnum = 0; $$.type = BWRITERSPR_MISCTYPE;
                        }
                    | REG_VFACE
                        {
                            $$.regnum = 1; $$.type = BWRITERSPR_MISCTYPE;
                        }
                    | REG_ADDRESS
                        {
                            $$.regnum = 0; $$.type = BWRITERSPR_ADDR;
                        }
                    | REG_LOOP
                        {
                            $$.regnum = 0; $$.type = BWRITERSPR_LOOP;
                        }
                    | REG_LABEL
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_LABEL;
                        }
1537

1538 1539 1540 1541 1542 1543 1544
comp:                 COMP_GT           { $$ = BWRITER_COMPARISON_GT;       }
                    | COMP_LT           { $$ = BWRITER_COMPARISON_LT;       }
                    | COMP_GE           { $$ = BWRITER_COMPARISON_GE;       }
                    | COMP_LE           { $$ = BWRITER_COMPARISON_LE;       }
                    | COMP_EQ           { $$ = BWRITER_COMPARISON_EQ;       }
                    | COMP_NE           { $$ = BWRITER_COMPARISON_NE;       }

1545 1546 1547 1548 1549 1550
dclusage:             USAGE_POSITION
                        {
                            TRACE("dcl_position%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_POSITION;
                        }
1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628
                    | USAGE_BLENDWEIGHT
                        {
                            TRACE("dcl_blendweight%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_BLENDWEIGHT;
                        }
                    | USAGE_BLENDINDICES
                        {
                            TRACE("dcl_blendindices%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_BLENDINDICES;
                        }
                    | USAGE_NORMAL
                        {
                            TRACE("dcl_normal%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_NORMAL;
                        }
                    | USAGE_PSIZE
                        {
                            TRACE("dcl_psize%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_PSIZE;
                        }
                    | USAGE_TEXCOORD
                        {
                            TRACE("dcl_texcoord%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_TEXCOORD;
                        }
                    | USAGE_TANGENT
                        {
                            TRACE("dcl_tangent%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_TANGENT;
                        }
                    | USAGE_BINORMAL
                        {
                            TRACE("dcl_binormal%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_BINORMAL;
                        }
                    | USAGE_TESSFACTOR
                        {
                            TRACE("dcl_tessfactor%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_TESSFACTOR;
                        }
                    | USAGE_POSITIONT
                        {
                            TRACE("dcl_positiont%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_POSITIONT;
                        }
                    | USAGE_COLOR
                        {
                            TRACE("dcl_color%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_COLOR;
                        }
                    | USAGE_FOG
                        {
                            TRACE("dcl_fog%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_FOG;
                        }
                    | USAGE_DEPTH
                        {
                            TRACE("dcl_depth%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_DEPTH;
                        }
                    | USAGE_SAMPLE
                        {
                            TRACE("dcl_sample%u\n", $1);
                            $$.regnum = $1;
                            $$.dclusage = BWRITERDECLUSAGE_SAMPLE;
                        }
1629

1630 1631 1632 1633 1634 1635 1636 1637 1638
dcl_inputreg:         REG_INPUT
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_INPUT;
                        }
                    | REG_TEXTURE
                        {
                            $$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
                        }

1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655
sampdcl:              SAMPTYPE_1D
                        {
                            $$ = BWRITERSTT_1D;
                        }
                    | SAMPTYPE_2D
                        {
                            $$ = BWRITERSTT_2D;
                        }
                    | SAMPTYPE_CUBE
                        {
                            $$ = BWRITERSTT_CUBE;
                        }
                    | SAMPTYPE_VOLUME
                        {
                            $$ = BWRITERSTT_VOLUME;
                        }

1656 1657 1658 1659 1660 1661
predicate:            '(' REG_PREDICATE swizzle ')'
                        {
                            $$.type = BWRITERSPR_PREDICATE;
                            $$.regnum = 0;
                            $$.rel_reg = NULL;
                            $$.srcmod = BWRITERSPSM_NONE;
1662
                            $$.u.swizzle = $3;
1663 1664 1665 1666 1667 1668 1669
                        }
                    | '(' SMOD_NOT REG_PREDICATE swizzle ')'
                        {
                            $$.type = BWRITERSPR_PREDICATE;
                            $$.regnum = 0;
                            $$.rel_reg = NULL;
                            $$.srcmod = BWRITERSPSM_NOT;
1670
                            $$.u.swizzle = $4;
1671 1672
                        }

1673 1674
%%

1675 1676
struct bwriter_shader *parse_asm_shader(char **messages)
{
1677 1678 1679 1680
    struct bwriter_shader *ret = NULL;

    asm_ctx.shader = NULL;
    asm_ctx.status = PARSE_SUCCESS;
1681
    asm_ctx.messages.size = asm_ctx.messages.capacity = 0;
1682 1683 1684 1685
    asm_ctx.line_no = 1;

    asmshader_parse();

1686 1687 1688 1689
    if (asm_ctx.status != PARSE_ERR)
        ret = asm_ctx.shader;
    else if (asm_ctx.shader)
        SlDeleteShader(asm_ctx.shader);
1690

1691 1692 1693 1694
    if (messages)
    {
        if (asm_ctx.messages.size)
        {
1695
            /* Shrink the buffer to the used size */
1696 1697 1698
            *messages = d3dcompiler_realloc(asm_ctx.messages.string, asm_ctx.messages.size + 1);
            if (!*messages)
            {
1699
                ERR("Out of memory, no messages reported\n");
1700
                d3dcompiler_free(asm_ctx.messages.string);
1701
            }
1702 1703 1704
        }
        else
        {
1705 1706
            *messages = NULL;
        }
1707 1708 1709 1710 1711
    }
    else
    {
        if (asm_ctx.messages.capacity)
            d3dcompiler_free(asm_ctx.messages.string);
1712 1713 1714 1715
    }

    return ret;
}